From: Alex Deucher <alexander.deucher@amd.com>
To: <amd-gfx@lists.freedesktop.org>
Cc: Asad Kamal <asad.kamal@amd.com>, Lijo Lazar <lijo.lazar@amd.com>,
"Alex Deucher" <alexander.deucher@amd.com>
Subject: [PATCH 08/25] drm/amd/pm: Update dpm table structs for smu_v15_0
Date: Tue, 17 Mar 2026 16:12:24 -0400 [thread overview]
Message-ID: <20260317201242.3808136-8-alexander.deucher@amd.com> (raw)
In-Reply-To: <20260317201242.3808136-1-alexander.deucher@amd.com>
From: Asad Kamal <asad.kamal@amd.com>
Update dpm table structs to use common definitions for smu_15_0
Signed-off-by: Asad Kamal <asad.kamal@amd.com>
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/pm/swsmu/inc/smu_v15_0.h | 47 +++--------
.../gpu/drm/amd/pm/swsmu/smu15/smu_v15_0.c | 79 +++++++++----------
2 files changed, 49 insertions(+), 77 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v15_0.h b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v15_0.h
index 06842d38c92bd..3c8c086f0f9d8 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v15_0.h
+++ b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v15_0.h
@@ -45,7 +45,6 @@
#define FEATURE_MASK(feature) (1ULL << feature)
-#define MAX_DPM_LEVELS 16
#define MAX_PCIE_CONF 3
#define SMU15_TOOL_SIZE 0x19000
@@ -69,39 +68,19 @@ struct smu_15_0_max_sustainable_clocks {
uint32_t soc_clock;
};
-struct smu_15_0_dpm_clk_level {
- bool enabled;
- uint32_t value;
-};
-
-struct smu_15_0_dpm_table {
- uint32_t min; /* MHz */
- uint32_t max; /* MHz */
- uint32_t count;
- bool is_fine_grained;
- struct smu_15_0_dpm_clk_level dpm_levels[MAX_DPM_LEVELS];
-};
-
-struct smu_15_0_pcie_table {
- uint8_t pcie_gen[MAX_PCIE_CONF];
- uint8_t pcie_lane[MAX_PCIE_CONF];
- uint16_t clk_freq[MAX_PCIE_CONF];
- uint32_t num_of_link_levels;
-};
-
struct smu_15_0_dpm_tables {
- struct smu_15_0_dpm_table soc_table;
- struct smu_15_0_dpm_table gfx_table;
- struct smu_15_0_dpm_table uclk_table;
- struct smu_15_0_dpm_table eclk_table;
- struct smu_15_0_dpm_table vclk_table;
- struct smu_15_0_dpm_table dclk_table;
- struct smu_15_0_dpm_table dcef_table;
- struct smu_15_0_dpm_table pixel_table;
- struct smu_15_0_dpm_table display_table;
- struct smu_15_0_dpm_table phy_table;
- struct smu_15_0_dpm_table fclk_table;
- struct smu_15_0_pcie_table pcie_table;
+ struct smu_dpm_table soc_table;
+ struct smu_dpm_table gfx_table;
+ struct smu_dpm_table uclk_table;
+ struct smu_dpm_table eclk_table;
+ struct smu_dpm_table vclk_table;
+ struct smu_dpm_table dclk_table;
+ struct smu_dpm_table dcef_table;
+ struct smu_dpm_table pixel_table;
+ struct smu_dpm_table display_table;
+ struct smu_dpm_table phy_table;
+ struct smu_dpm_table fclk_table;
+ struct smu_pcie_table pcie_table;
};
struct smu_15_0_dpm_context {
@@ -204,7 +183,7 @@ int smu_v15_0_set_power_source(struct smu_context *smu,
int smu_v15_0_set_single_dpm_table(struct smu_context *smu,
enum smu_clk_type clk_type,
- struct smu_15_0_dpm_table *single_dpm_table);
+ struct smu_dpm_table *single_dpm_table);
int smu_v15_0_gfx_ulv_control(struct smu_context *smu,
bool enablement);
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0.c b/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0.c
index 51d1f5d42ad31..a9417cb4e920b 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0.c
@@ -1059,18 +1059,12 @@ int smu_v15_0_set_performance_level(struct smu_context *smu,
{
struct smu_15_0_dpm_context *dpm_context =
smu->smu_dpm.dpm_context;
- struct smu_15_0_dpm_table *gfx_table =
- &dpm_context->dpm_tables.gfx_table;
- struct smu_15_0_dpm_table *mem_table =
- &dpm_context->dpm_tables.uclk_table;
- struct smu_15_0_dpm_table *soc_table =
- &dpm_context->dpm_tables.soc_table;
- struct smu_15_0_dpm_table *vclk_table =
- &dpm_context->dpm_tables.vclk_table;
- struct smu_15_0_dpm_table *dclk_table =
- &dpm_context->dpm_tables.dclk_table;
- struct smu_15_0_dpm_table *fclk_table =
- &dpm_context->dpm_tables.fclk_table;
+ struct smu_dpm_table *gfx_table = &dpm_context->dpm_tables.gfx_table;
+ struct smu_dpm_table *mem_table = &dpm_context->dpm_tables.uclk_table;
+ struct smu_dpm_table *soc_table = &dpm_context->dpm_tables.soc_table;
+ struct smu_dpm_table *vclk_table = &dpm_context->dpm_tables.vclk_table;
+ struct smu_dpm_table *dclk_table = &dpm_context->dpm_tables.dclk_table;
+ struct smu_dpm_table *fclk_table = &dpm_context->dpm_tables.fclk_table;
struct smu_umd_pstate_table *pstate_table =
&smu->pstate_table;
struct amdgpu_device *adev = smu->adev;
@@ -1085,34 +1079,34 @@ int smu_v15_0_set_performance_level(struct smu_context *smu,
switch (level) {
case AMD_DPM_FORCED_LEVEL_HIGH:
- sclk_min = sclk_max = gfx_table->max;
- mclk_min = mclk_max = mem_table->max;
- socclk_min = socclk_max = soc_table->max;
- vclk_min = vclk_max = vclk_table->max;
- dclk_min = dclk_max = dclk_table->max;
- fclk_min = fclk_max = fclk_table->max;
+ sclk_min = sclk_max = SMU_DPM_TABLE_MAX(gfx_table);
+ mclk_min = mclk_max = SMU_DPM_TABLE_MAX(mem_table);
+ socclk_min = socclk_max = SMU_DPM_TABLE_MAX(soc_table);
+ vclk_min = vclk_max = SMU_DPM_TABLE_MAX(vclk_table);
+ dclk_min = dclk_max = SMU_DPM_TABLE_MAX(dclk_table);
+ fclk_min = fclk_max = SMU_DPM_TABLE_MAX(fclk_table);
break;
case AMD_DPM_FORCED_LEVEL_LOW:
- sclk_min = sclk_max = gfx_table->min;
- mclk_min = mclk_max = mem_table->min;
- socclk_min = socclk_max = soc_table->min;
- vclk_min = vclk_max = vclk_table->min;
- dclk_min = dclk_max = dclk_table->min;
- fclk_min = fclk_max = fclk_table->min;
+ sclk_min = sclk_max = SMU_DPM_TABLE_MIN(gfx_table);
+ mclk_min = mclk_max = SMU_DPM_TABLE_MIN(mem_table);
+ socclk_min = socclk_max = SMU_DPM_TABLE_MIN(soc_table);
+ vclk_min = vclk_max = SMU_DPM_TABLE_MIN(vclk_table);
+ dclk_min = dclk_max = SMU_DPM_TABLE_MIN(dclk_table);
+ fclk_min = fclk_max = SMU_DPM_TABLE_MIN(fclk_table);
break;
case AMD_DPM_FORCED_LEVEL_AUTO:
- sclk_min = gfx_table->min;
- sclk_max = gfx_table->max;
- mclk_min = mem_table->min;
- mclk_max = mem_table->max;
- socclk_min = soc_table->min;
- socclk_max = soc_table->max;
- vclk_min = vclk_table->min;
- vclk_max = vclk_table->max;
- dclk_min = dclk_table->min;
- dclk_max = dclk_table->max;
- fclk_min = fclk_table->min;
- fclk_max = fclk_table->max;
+ sclk_min = SMU_DPM_TABLE_MIN(gfx_table);
+ sclk_max = SMU_DPM_TABLE_MAX(gfx_table);
+ mclk_min = SMU_DPM_TABLE_MIN(mem_table);
+ mclk_max = SMU_DPM_TABLE_MAX(mem_table);
+ socclk_min = SMU_DPM_TABLE_MIN(soc_table);
+ socclk_max = SMU_DPM_TABLE_MAX(soc_table);
+ vclk_min = SMU_DPM_TABLE_MIN(vclk_table);
+ vclk_max = SMU_DPM_TABLE_MAX(vclk_table);
+ dclk_min = SMU_DPM_TABLE_MIN(dclk_table);
+ dclk_max = SMU_DPM_TABLE_MAX(dclk_table);
+ fclk_min = SMU_DPM_TABLE_MIN(fclk_table);
+ fclk_max = SMU_DPM_TABLE_MAX(fclk_table);
auto_level = true;
break;
case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
@@ -1334,10 +1328,11 @@ static int smu_v15_0_get_fine_grained_status(struct smu_context *smu,
int smu_v15_0_set_single_dpm_table(struct smu_context *smu,
enum smu_clk_type clk_type,
- struct smu_15_0_dpm_table *single_dpm_table)
+ struct smu_dpm_table *single_dpm_table)
{
int ret = 0;
uint32_t clk;
+ bool is_fine_grained;
int i;
ret = smu_v15_0_get_dpm_level_count(smu,
@@ -1350,12 +1345,15 @@ int smu_v15_0_set_single_dpm_table(struct smu_context *smu,
ret = smu_v15_0_get_fine_grained_status(smu,
clk_type,
- &single_dpm_table->is_fine_grained);
+ &is_fine_grained);
if (ret) {
dev_err(smu->adev->dev, "[%s] failed to get fine grained status!\n", __func__);
return ret;
}
+ if (is_fine_grained)
+ single_dpm_table->flags |= SMU_DPM_TABLE_FINE_GRAINED;
+
for (i = 0; i < single_dpm_table->count; i++) {
ret = smu_v15_0_get_dpm_freq_by_index(smu,
clk_type,
@@ -1368,11 +1366,6 @@ int smu_v15_0_set_single_dpm_table(struct smu_context *smu,
single_dpm_table->dpm_levels[i].value = clk;
single_dpm_table->dpm_levels[i].enabled = true;
-
- if (i == 0)
- single_dpm_table->min = clk;
- else if (i == single_dpm_table->count - 1)
- single_dpm_table->max = clk;
}
return 0;
--
2.53.0
next prev parent reply other threads:[~2026-03-17 20:13 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-03-17 20:12 [PATCH 01/25] drm/amd/pm: Add smu v15_0_8 driver interface header Alex Deucher
2026-03-17 20:12 ` [PATCH 02/25] drm/amd/pm: Add smu v15_0_8 message header Alex Deucher
2026-03-17 20:12 ` [PATCH 03/25] drm/amd/pm: Add smu v15_0_8 pmfw header Alex Deucher
2026-03-17 20:12 ` [PATCH 04/25] drm/amd/pm: Add initial support for smu v15_0_8 Alex Deucher
2026-03-17 20:12 ` [PATCH 05/25] drm/amd/pm: Add mode2 support for smu_v15_0_8 Alex Deucher
2026-03-17 20:12 ` [PATCH 06/25] drm/amd/pm: Add static metrics support Alex Deucher
2026-03-17 20:12 ` [PATCH 07/25] drm/amd/pm: Setup driver pptable for smu 15.0.8 Alex Deucher
2026-03-17 20:12 ` Alex Deucher [this message]
2026-03-17 20:12 ` [PATCH 09/25] drm/amd/pm: Add default dpm table support " Alex Deucher
2026-03-17 20:12 ` [PATCH 10/25] drm/amd/pm: Add get_pm_metrics " Alex Deucher
2026-03-17 20:12 ` [PATCH 11/25] drm/amd/pm: add get_gpu_metrics support for 15.0.8 Alex Deucher
2026-03-17 20:12 ` [PATCH 12/25] drm/amd/pm: add get_unique_id support for smu 15.0.8 Alex Deucher
2026-03-17 20:12 ` [PATCH 13/25] drm/amd/pm: add set{get}_power_limit " Alex Deucher
2026-03-17 20:12 ` [PATCH 14/25] drm/amd/pm: Add emit clock support Alex Deucher
2026-03-17 20:12 ` [PATCH 15/25] drm/amd/pm: add populate_umd_state_clk support Alex Deucher
2026-03-17 20:12 ` [PATCH 16/25] drm/amd/pm: Add set_performance_support Alex Deucher
2026-03-17 20:12 ` [PATCH 17/25] drm/amd/pm: Add od_edit_dpm_table support Alex Deucher
2026-03-17 20:12 ` [PATCH 18/25] drm/amd/pm: Add get_thermal_temperature_range support Alex Deucher
2026-03-17 20:12 ` [PATCH 19/25] drm/amd/pm: Add ppt1 support Alex Deucher
2026-03-17 20:12 ` [PATCH 20/25] drm/amd/pm: Add read sensor support Alex Deucher
2026-03-17 20:12 ` [PATCH 21/25] drm/amd/pm: Add gpuboard temperature metrics support Alex Deucher
2026-03-17 20:12 ` [PATCH 22/25] drm/amd/pm: Add baseboard " Alex Deucher
2026-03-17 20:12 ` [PATCH 23/25] drm/amd/pm: Add NPM support for smu_v15_0_8 Alex Deucher
2026-03-17 20:12 ` [PATCH 24/25] drm/amdgpu: Add smu v15_0_8 ip block Alex Deucher
2026-03-17 20:12 ` [PATCH 25/25] drm/amd/pm: Enable user specified gfx clock ranges Alex Deucher
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