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Wed, 18 Mar 2026 09:08:55 -0500 From: Alex Deucher To: CC: Alex Deucher Subject: [PATCH 01/16] drm/amdgpu/gfx7: align mqd settings with KFD Date: Wed, 18 Mar 2026 10:08:22 -0400 Message-ID: <20260318140837.582776-1-alexander.deucher@amd.com> X-Mailer: git-send-email 2.53.0 MIME-Version: 1.0 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 8bit X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF00012E65:EE_|CH2PR12MB4070:EE_ X-MS-Office365-Filtering-Correlation-Id: 0dbb902e-dd8f-4983-dafa-08de84f7e540 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|376014|82310400026|36860700016|1800799024|56012099003|18002099003; X-Microsoft-Antispam-Message-Info: T4aKHcEsgDPA5QGIOGHeRHWPuJjO4zlv/8j/DnIro2CRgms8KMP5p+3rXYX1v5qbiHVvyaZPhb0ESSwkTpQ+7p2Lx9SGsV1qoojdMKWH1mLBcDE0ul3TjOmtKXc4F9P5hI7bkRS+GZyAWGxzGj6mJUG7cd2OWqVTk7hmGoa/ki9VZ/IYCxxz+r6kJWwmxDDwyTHjSXniLVjMO7YsKIaOrTQrYkcAznRte3KYIhx9UrEM5v/KjEr/euR1kY3Ah1kNx5F1pPE8zcxwQ298sD0k1XoXY/JQUr2O6WG7vT1/2tVSLypXjNiEx4IAy3knZQcpyXGGmHUc3Ki3HwbY1UVpF2KlGy/fWUYk/BwfibPDKPytqSbjagUIBlBJGt1k0Z2vXtMipcEJO6StjBKpVnrUTt3IhoV2Hd7XoeAAiDOrofmTi2I/3BH+LuUrVvO7yPV7zMTGa0vDKAjUYpkPmD4pvFkzSFH9qtUywZLTtUjjxYOPANNuCR9Ggtby53TE4yv5bhgS5lyxfHsFA6MPNWE11AQLfT4wdhAjxE6VMuVsyNzsKceuaRNz986UYpRGT4w50Qn6Vi3F8YteCHDAPet4p2iIfCzD4UpJJOu0CIaY4WssYfaTWVIPSryoKWkHW4iaMQRMO8vqfXENSoMUd/JZafrQKciN54SzUHV7qJFvHqNMNAWEud+/rXTxPWnAmrm3WvhKJqkTDK8M58/IIyogV0+UHSEC6iRSUQyf5cP0SNmxCqGnuBiQ9+jOx7kqTaJ6+EBaUo1M+4svqzVnhdADcw== X-Forefront-Antispam-Report: CIP:165.204.84.17; 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Ip=[165.204.84.17]; Helo=[satlexmb08.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF00012E65.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH2PR12MB4070 X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" Make sure to set the quantum bits in the compute MQD for better fairness across queues of the same priority. Reviewed-by：Jesse Zhang Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c index 2b691452775bc..65b8497ad5f02 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c @@ -2819,6 +2819,7 @@ static void gfx_v7_0_mqd_init(struct amdgpu_device *adev, { u64 hqd_gpu_addr; u64 wb_gpu_addr; + u32 tmp; /* init the mqd struct */ memset(mqd, 0, sizeof(struct cik_mqd)); @@ -2923,7 +2924,11 @@ static void gfx_v7_0_mqd_init(struct amdgpu_device *adev, mqd->cp_hqd_atomic1_preop_lo = RREG32(mmCP_HQD_ATOMIC1_PREOP_LO); mqd->cp_hqd_atomic1_preop_hi = RREG32(mmCP_HQD_ATOMIC1_PREOP_HI); mqd->cp_hqd_pq_rptr = RREG32(mmCP_HQD_PQ_RPTR); - mqd->cp_hqd_quantum = RREG32(mmCP_HQD_QUANTUM); + tmp = RREG32(mmCP_HQD_QUANTUM); + tmp = REG_SET_FIELD(tmp, CP_HQD_QUANTUM, QUANTUM_EN, 1); + tmp = REG_SET_FIELD(tmp, CP_HQD_QUANTUM, QUANTUM_SCALE, 1); + tmp = REG_SET_FIELD(tmp, CP_HQD_QUANTUM, QUANTUM_DURATION, 10); + mqd->cp_hqd_quantum = tmp; mqd->cp_hqd_pipe_priority = RREG32(mmCP_HQD_PIPE_PRIORITY); mqd->cp_hqd_queue_priority = RREG32(mmCP_HQD_QUEUE_PRIORITY); mqd->cp_hqd_iq_rptr = RREG32(mmCP_HQD_IQ_RPTR); -- 2.53.0