[PATCH 2/4] drm/amdgpu/sdma6: program quantums

[Alex Deucher <alexander.deucher@amd.com>]

Set the quantums for queue switching on the instance.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c | 32 ++++++++++++++++++++++++++
 1 file changed, 32 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c
index b005672f2f96b..3af5bf0f18426 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c
@@ -505,6 +505,38 @@ static int sdma_v6_0_gfx_resume_instance(struct amdgpu_device *adev, int i, bool
 	rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RB_PRIV, 1);
 	WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL), rb_cntl);
 
+	/* handle queue priority and quantums */
+	temp = REG_SET_FIELD(0, SDMA0_QUEUE0_SCHEDULE_CNTL, GLOBAL_ID, 2); /* 3-0, 3 is highest priority */
+	temp = REG_SET_FIELD(temp, SDMA0_QUEUE0_SCHEDULE_CNTL, CONTEXT_QUANTUM,
+			     AMDGPU_SDMA_CONTEXT_QUANTUM); /*  value * 100us */
+	WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_SCHEDULE_CNTL), temp);
+
+	temp = REG_SET_FIELD(0, SDMA0_GLOBAL_QUANTUM, GLOBAL_FOCUS_QUANTUM,
+			     AMDGPU_SDMA_FOCUS_QUANTUM); /*  value * 100us */
+	temp = REG_SET_FIELD(temp, SDMA0_GLOBAL_QUANTUM, GLOBAL_NORMAL_QUANTUM,
+			     AMDGPU_SDMA_NORMAL_QUANTUM); /*  value * 100us */
+	WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_GLOBAL_QUANTUM), temp);
+
+	temp = REG_SET_FIELD(0, SDMA0_PROCESS_QUANTUM0, PROCESS0_QUANTUM,
+			     AMDGPU_SDMA_PROCESS_QUANTUM); /*  value * 100us */
+	temp = REG_SET_FIELD(temp, SDMA0_PROCESS_QUANTUM0, PROCESS1_QUANTUM,
+			     AMDGPU_SDMA_PROCESS_QUANTUM); /*  value * 100us */
+	temp = REG_SET_FIELD(temp, SDMA0_PROCESS_QUANTUM0, PROCESS2_QUANTUM,
+			     AMDGPU_SDMA_PROCESS_QUANTUM); /*  value * 100us */
+	temp = REG_SET_FIELD(temp, SDMA0_PROCESS_QUANTUM0, PROCESS3_QUANTUM,
+			     AMDGPU_SDMA_PROCESS_QUANTUM); /*  value * 100us */
+	WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_PROCESS_QUANTUM0), temp);
+
+	temp = REG_SET_FIELD(0, SDMA0_PROCESS_QUANTUM1, PROCESS4_QUANTUM,
+			     AMDGPU_SDMA_PROCESS_QUANTUM); /*  value * 100us */
+	temp = REG_SET_FIELD(temp, SDMA0_PROCESS_QUANTUM1, PROCESS5_QUANTUM,
+			     AMDGPU_SDMA_PROCESS_QUANTUM); /*  value * 100us */
+	temp = REG_SET_FIELD(temp, SDMA0_PROCESS_QUANTUM1, PROCESS6_QUANTUM,
+			     AMDGPU_SDMA_PROCESS_QUANTUM); /*  value * 100us */
+	temp = REG_SET_FIELD(temp, SDMA0_PROCESS_QUANTUM1, PROCESS7_QUANTUM,
+			     AMDGPU_SDMA_PROCESS_QUANTUM); /*  value * 100us */
+	WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_PROCESS_QUANTUM1), temp);
+
 	/* Initialize the ring buffer's read and write pointers */
 	if (restore) {
 		WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR), lower_32_bits(ring->wptr << 2));
-- 
2.53.0