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Thu, 26 Mar 2026 07:29:36 -0500 From: Benjamin Cheng To: Alex Deucher , =?UTF-8?q?Christian=20K=C3=B6nig?= , CC: Leo Liu , Ruijing Dong , "David (Ming Qiang) Wu" , Benjamin Cheng Subject: [PATCH v2 1/4] drm/amdgpu: Add bounds checking to ib_{get,set}_value Date: Thu, 26 Mar 2026 08:29:16 -0400 Message-ID: <20260326122918.3486416-2-benjamin.cheng@amd.com> X-Mailer: git-send-email 2.53.0 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF000023CB:EE_|MW3PR12MB4475:EE_ X-MS-Office365-Filtering-Correlation-Id: c17c9556-95be-4b41-80ff-08de8b335867 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|376014|82310400026|1800799024|36860700016|56012099003|18002099003; X-Microsoft-Antispam-Message-Info: 2zS0XmiyGuONT17WNRBcUDaoKOlvP3C1Jx/LCjAqRd98DrjV6THpbXV6EKxYHb00AhWl9O2f4bTFh3ldo3lw7Hf4iOO/VPAgUHDUp5NLoOQ2cMmN2qjVjDIbJo7QnoKr02566UJHxiEbT1Y9R/+6YJVdeUtka8ukjTjwMt+Lr5EHPWT3DUUEvi5Djlj6L+nWd3g5Xx0Nhk1GMDZZdmEKm0K71EZkudAVqlqlk+Xd7Z1bJCDM+dXgvhK4se5fCRyywDNUd0MOTiZlHCyb2CesKlFrkZ7A2YjG6qh3mAC2onvmyNF4ZmGL1SpLkHCo2lX68OCrBsud5aEoEK81/7MaEld98kmNhZil2RDL1G4oewmxUnw5dXtDJUjZp8+BxC7nc/YG/bxRE/GowBWxWDjlNUBjRbePbCUCOjangilQGnm9hrxnFaQNX3z6VxJbSoCFNfMCfrO6IqDM2MHPDYCBXhvqFnRXpZlKu3NChrNyp1gn1Ym/U8u1Pdvdrd5tlEoE5wn7wg1KnyqclhDDQ9ekmkaOlTtw2d/x+K9jH2NvfMpZnJUf+NnXoaEAyJpz+0OoerAwd2GfHvjfxc5vCnD/mtkLfRniA6Xqkiu976QsvqqsEMxl2iZc7akdfpM6zTShVubfcGI2z7phacGS9v43CJ++3PbmqDftkJnTNgzTUCV9KDAVcBOEgDKxr1+IZJuxMyaVrHTgUeNsjvwSHYaaZ6dDsSAEb3k/X22kseG2Rlu1+dsd3Q6UospZ4mGEtJazqodqgxQ2lhC3EUqK5AfiVw== X-Forefront-Antispam-Report: CIP:165.204.84.17; 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Ip=[165.204.84.17]; Helo=[satlexmb08.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF000023CB.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW3PR12MB4475 X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" The uvd/vce/vcn code accesses the IB at predefined offsets without checking that the IB is large enough. Check the bounds here. The caller is responsible for making sure it can handle arbitrary return values. Also make the idx a uint32_t to prevent overflows causing the condition to fail. Signed-off-by: Benjamin Cheng --- drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h index ce5af137ee40..715c9e43e13a 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h @@ -559,15 +559,18 @@ void amdgpu_debugfs_ring_init(struct amdgpu_device *adev, int amdgpu_ring_init_mqd(struct amdgpu_ring *ring); -static inline u32 amdgpu_ib_get_value(struct amdgpu_ib *ib, int idx) +static inline u32 amdgpu_ib_get_value(struct amdgpu_ib *ib, uint32_t idx) { - return ib->ptr[idx]; + if (idx < ib->length_dw) + return ib->ptr[idx]; + return 0; } -static inline void amdgpu_ib_set_value(struct amdgpu_ib *ib, int idx, +static inline void amdgpu_ib_set_value(struct amdgpu_ib *ib, uint32_t idx, uint32_t value) { - ib->ptr[idx] = value; + if (idx < ib->length_dw) + ib->ptr[idx] = value; } int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm, -- 2.53.0