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Tue, 7 Apr 2026 15:05:31 -0500 From: Benjamin Cheng To: Alex Deucher , =?UTF-8?q?Christian=20K=C3=B6nig?= , Leo Liu , CC: "David (Ming Qiang) Wu" , Ruijing Dong , Benjamin Cheng Subject: [PATCH] drm/amdgpu/vcn: Factor out vcn_v{3,4}_0_dec_msg Date: Tue, 7 Apr 2026 16:05:18 -0400 Message-ID: <20260407200518.911117-1-benjamin.cheng@amd.com> X-Mailer: git-send-email 2.53.0 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF000023D1:EE_|MN2PR12MB4470:EE_ X-MS-Office365-Filtering-Correlation-Id: 025f4fef-7fa5-4406-eec1-08de94e106a5 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|1800799024|36860700016|376014|82310400026|56012099003|18002099003; X-Microsoft-Antispam-Message-Info: EWU1Mqgn+/TjXj14BHfFEK6DBiJcxnacKcy12RtlVfDxfrIXpAgXDFwcHeuz9K2EuLrL/dOQ2JWQek/SrwFua8GD7qvJjAD0BVyraVurBz3ULiBiUNteTU3Y4YNcwcJULV9gF4tIooDwqO/buy2Ho5Y/fNVaXwAgh71d2P/cYIDJ0icaQJB86ZJL9CQ5KGb/dK89m868VQZwsfM4REeevbECXW2/XfH7dzGM6ETNE9tUhBKm5GyWCFlDHBF/cz0gkVgiY3mnjpqIKjUsJ1dlfJ3AoQs83fVXAAV6810SSiMkQ6ijIBY8pD6gOA4VgqNmqoCQG45w5rONqQzJrHkpUa/9ukIAy1cNs4OkFdE/A53Lb+mYelCzYMXA6G7PQRktdCm3b/p02B5nVod4WsgVT94U/+DMLLZorJQoQFmJuCePSHDWSNrNrwYvaWdHtNGlkOooi1UXv8BB9VcNatqNaIQ4wKoK5XKUBR3xoB34zPjjL7S2fbynaBMc9VjcXbsrrqjWdq1FB59XR8hbDMnXW+3xXgPDRlBHcYuCHNWe7uqqkkhbCPfVm7GPyDMNkMzTzG7L3Fvn6FG0G9uCZF1HEkOZOvHjahjIb5u9n88vxjVlWC7IX/nVrn2+z2mZax6oBsuZcMswWcXDnTA7r8TZXNYhZSdnUSy+vDRavzS9ORYXlBZGKEsvTUD7trnNC8VGyZbYGzJp/i72AZBG4PSJP/LE2dsS5JgdhcMJ6ziIm1b5ghUsaIq7ejYcnJyWlEvoVka5Hjk7UyMtlcnijfP1gg== X-Forefront-Antispam-Report: CIP:165.204.84.17; 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Ip=[165.204.84.17]; Helo=[satlexmb08.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF000023D1.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4470 X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" Both vcn_v3_0 and vcn_v4_0 use the same interface, so unify the code. Signed-off-by: Benjamin Cheng --- drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 103 +++++++++++++++++++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h | 5 ++ drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c | 105 +----------------------- drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c | 104 +---------------------- 4 files changed, 112 insertions(+), 205 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c index 03d95dca93d7..910dd5bd1ab6 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c @@ -36,6 +36,9 @@ #include "amdgpu_vcn.h" #include "soc15d.h" +#define RDECODE_MSG_CREATE 0x00000000 +#define RDECODE_MESSAGE_CREATE 0x00000001 + /* Firmware Names */ #define FIRMWARE_RAVEN "amdgpu/raven_vcn.bin" #define FIRMWARE_PICASSO "amdgpu/picasso_vcn.bin" @@ -1641,3 +1644,103 @@ void amdgpu_vcn_print_ip_state(struct amdgpu_ip_block *ip_block, struct drm_prin } } } + +int amdgpu_vcn_dec_msg_limit_sched(struct amdgpu_cs_parser *p, + struct amdgpu_job *job, uint64_t addr, + int (*limit_sched)(struct amdgpu_cs_parser *, + struct amdgpu_job *)) +{ + struct ttm_operation_ctx ctx = { false, false }; + struct amdgpu_device *adev = p->adev; + struct amdgpu_bo_va_mapping *map; + uint32_t *msg, num_buffers, len_dw; + struct amdgpu_bo *bo; + uint64_t start, end; + unsigned int i; + void *ptr; + int r; + + addr &= AMDGPU_GMC_HOLE_MASK; + r = amdgpu_cs_find_mapping(p, addr, &bo, &map); + if (r) { + DRM_ERROR("Can't find BO for addr 0x%08llx\n", addr); + return r; + } + + start = map->start * AMDGPU_GPU_PAGE_SIZE; + end = (map->last + 1) * AMDGPU_GPU_PAGE_SIZE; + if (addr & 0x7) { + DRM_ERROR("VCN messages must be 8 byte aligned!\n"); + return -EINVAL; + } + + if (end - addr < 16) { + DRM_ERROR("VCN messages must be at least 4 DWORDs!\n"); + return -EINVAL; + } + + bo->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; + amdgpu_bo_placement_from_domain(bo, bo->allowed_domains); + r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); + if (r) { + DRM_ERROR("Failed validating the VCN message BO (%d)!\n", r); + return r; + } + + r = amdgpu_bo_kmap(bo, &ptr); + if (r) { + DRM_ERROR("Failed mapping the VCN message (%d)!\n", r); + return r; + } + + msg = ptr + addr - start; + + if (msg[1] > end - addr) { + DRM_ERROR("VCN message header does not fit in BO!\n"); + r = -EINVAL; + goto out; + } + + if (msg[3] != RDECODE_MSG_CREATE) + goto out; + + len_dw = msg[1] / 4; + num_buffers = msg[2]; + + /* Verify that all indices fit within the claimed length. Each index is 4 DWORDs */ + if (num_buffers > len_dw || 6 + num_buffers * 4 > len_dw) { + DRM_ERROR("VCN message has too many buffers!\n"); + r = -EINVAL; + goto out; + } + + for (i = 0, msg = &msg[6]; i < num_buffers; ++i, msg += 4) { + uint32_t offset, size, *create; + + if (msg[0] != RDECODE_MESSAGE_CREATE) + continue; + + offset = msg[1]; + size = msg[2]; + + if (size < 4 || offset + size > end - addr) { + DRM_ERROR("VCN message buffer exceeds BO bounds!\n"); + r = -EINVAL; + goto out; + } + + create = ptr + addr + offset - start; + + /* H264, HEVC and VP9 can run on any instance */ + if (create[0] == 0x7 || create[0] == 0x10 || create[0] == 0x11) + continue; + + r = limit_sched(p, job); + if (r) + goto out; + } + +out: + amdgpu_bo_kunmap(bo); + return r; +} diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h index 82624b44e661..64f27de1a6f0 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h @@ -570,4 +570,9 @@ void amdgpu_vcn_print_ip_state(struct amdgpu_ip_block *ip_block, struct drm_prin void amdgpu_vcn_get_profile(struct amdgpu_device *adev); void amdgpu_vcn_put_profile(struct amdgpu_device *adev); +int amdgpu_vcn_dec_msg_limit_sched(struct amdgpu_cs_parser *p, struct amdgpu_job *job, + uint64_t addr, + int (*limit_sched)(struct amdgpu_cs_parser *, + struct amdgpu_job *)); + #endif diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c index 6fb4fcdbba4f..38a4fcf5872e 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c @@ -58,9 +58,6 @@ #define VCN_INSTANCES_SIENNA_CICHLID 2 #define DEC_SW_RING_ENABLED FALSE -#define RDECODE_MSG_CREATE 0x00000000 -#define RDECODE_MESSAGE_CREATE 0x00000001 - static const struct amdgpu_hwip_reg_entry vcn_reg_list_3_0[] = { SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_POWER_STATUS), SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_STATUS), @@ -1903,104 +1900,6 @@ static int vcn_v3_0_limit_sched(struct amdgpu_cs_parser *p, return 0; } -static int vcn_v3_0_dec_msg(struct amdgpu_cs_parser *p, struct amdgpu_job *job, - uint64_t addr) -{ - struct ttm_operation_ctx ctx = { false, false }; - struct amdgpu_device *adev = p->adev; - struct amdgpu_bo_va_mapping *map; - uint32_t *msg, num_buffers, len_dw; - struct amdgpu_bo *bo; - uint64_t start, end; - unsigned int i; - void *ptr; - int r; - - addr &= AMDGPU_GMC_HOLE_MASK; - r = amdgpu_cs_find_mapping(p, addr, &bo, &map); - if (r) { - DRM_ERROR("Can't find BO for addr 0x%08Lx\n", addr); - return r; - } - - start = map->start * AMDGPU_GPU_PAGE_SIZE; - end = (map->last + 1) * AMDGPU_GPU_PAGE_SIZE; - if (addr & 0x7) { - DRM_ERROR("VCN messages must be 8 byte aligned!\n"); - return -EINVAL; - } - - if (end - addr < 16) { - DRM_ERROR("VCN messages must be at least 4 DWORDs!\n"); - return -EINVAL; - } - - bo->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; - amdgpu_bo_placement_from_domain(bo, bo->allowed_domains); - r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); - if (r) { - DRM_ERROR("Failed validating the VCN message BO (%d)!\n", r); - return r; - } - - r = amdgpu_bo_kmap(bo, &ptr); - if (r) { - DRM_ERROR("Failed mapping the VCN message (%d)!\n", r); - return r; - } - - msg = ptr + addr - start; - - if (msg[1] > end - addr) { - DRM_ERROR("VCN message header does not fit in BO!\n"); - r = -EINVAL; - goto out; - } - - if (msg[3] != RDECODE_MSG_CREATE) - goto out; - - len_dw = msg[1] / 4; - num_buffers = msg[2]; - - /* Verify that all indices fit within the claimed length. Each index is 4 DWORDs */ - if (num_buffers > len_dw || 6 + num_buffers * 4 > len_dw) { - DRM_ERROR("VCN message has too many buffers!\n"); - r = -EINVAL; - goto out; - } - - for (i = 0, msg = &msg[6]; i < num_buffers; ++i, msg += 4) { - uint32_t offset, size, *create; - - if (msg[0] != RDECODE_MESSAGE_CREATE) - continue; - - offset = msg[1]; - size = msg[2]; - - if (size < 4 || offset + size > end - addr) { - DRM_ERROR("VCN message buffer exceeds BO bounds!\n"); - r = -EINVAL; - goto out; - } - - create = ptr + addr + offset - start; - - /* H264, HEVC and VP9 can run on any instance */ - if (create[0] == 0x7 || create[0] == 0x10 || create[0] == 0x11) - continue; - - r = vcn_v3_0_limit_sched(p, job); - if (r) - goto out; - } - -out: - amdgpu_bo_kunmap(bo); - return r; -} - static int vcn_v3_0_ring_patch_cs_in_place(struct amdgpu_cs_parser *p, struct amdgpu_job *job, struct amdgpu_ib *ib) @@ -2024,8 +1923,8 @@ static int vcn_v3_0_ring_patch_cs_in_place(struct amdgpu_cs_parser *p, msg_hi = val; } else if (reg == PACKET0(p->adev->vcn.inst[ring->me].internal.cmd, 0) && val == 0) { - r = vcn_v3_0_dec_msg(p, job, - ((u64)msg_hi) << 32 | msg_lo); + r = amdgpu_vcn_dec_msg_limit_sched(p, job, ((u64)msg_hi) << 32 | msg_lo, + vcn_v3_0_limit_sched); if (r) return r; } diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c index 5dec92691f73..41215ad7dfac 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c @@ -50,9 +50,6 @@ #define VCN_HARVEST_MMSCH 0 -#define RDECODE_MSG_CREATE 0x00000000 -#define RDECODE_MESSAGE_CREATE 0x00000001 - static const struct amdgpu_hwip_reg_entry vcn_reg_list_4_0[] = { SOC15_REG_ENTRY_STR(VCN, 0, regUVD_POWER_STATUS), SOC15_REG_ENTRY_STR(VCN, 0, regUVD_STATUS), @@ -1820,104 +1817,6 @@ static int vcn_v4_0_limit_sched(struct amdgpu_cs_parser *p, return 0; } -static int vcn_v4_0_dec_msg(struct amdgpu_cs_parser *p, struct amdgpu_job *job, - uint64_t addr) -{ - struct ttm_operation_ctx ctx = { false, false }; - struct amdgpu_device *adev = p->adev; - struct amdgpu_bo_va_mapping *map; - uint32_t *msg, num_buffers, len_dw; - struct amdgpu_bo *bo; - uint64_t start, end; - unsigned int i; - void *ptr; - int r; - - addr &= AMDGPU_GMC_HOLE_MASK; - r = amdgpu_cs_find_mapping(p, addr, &bo, &map); - if (r) { - DRM_ERROR("Can't find BO for addr 0x%08llx\n", addr); - return r; - } - - start = map->start * AMDGPU_GPU_PAGE_SIZE; - end = (map->last + 1) * AMDGPU_GPU_PAGE_SIZE; - if (addr & 0x7) { - DRM_ERROR("VCN messages must be 8 byte aligned!\n"); - return -EINVAL; - } - - if (end - addr < 16) { - DRM_ERROR("VCN messages must be at least 4 DWORDs!\n"); - return -EINVAL; - } - - bo->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; - amdgpu_bo_placement_from_domain(bo, bo->allowed_domains); - r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); - if (r) { - DRM_ERROR("Failed validating the VCN message BO (%d)!\n", r); - return r; - } - - r = amdgpu_bo_kmap(bo, &ptr); - if (r) { - DRM_ERROR("Failed mapping the VCN message (%d)!\n", r); - return r; - } - - msg = ptr + addr - start; - - if (msg[1] > end - addr) { - DRM_ERROR("VCN message header does not fit in BO!\n"); - r = -EINVAL; - goto out; - } - - if (msg[3] != RDECODE_MSG_CREATE) - goto out; - - len_dw = msg[1] / 4; - num_buffers = msg[2]; - - /* Verify that all indices fit within the claimed length. Each index is 4 DWORDs */ - if (num_buffers > len_dw || 6 + num_buffers * 4 > len_dw) { - DRM_ERROR("VCN message has too many buffers!\n"); - r = -EINVAL; - goto out; - } - - for (i = 0, msg = &msg[6]; i < num_buffers; ++i, msg += 4) { - uint32_t offset, size, *create; - - if (msg[0] != RDECODE_MESSAGE_CREATE) - continue; - - offset = msg[1]; - size = msg[2]; - - if (size < 4 || offset + size > end - addr) { - DRM_ERROR("VCN message buffer exceeds BO bounds!\n"); - r = -EINVAL; - goto out; - } - - create = ptr + addr + offset - start; - - /* H264, HEVC and VP9 can run on any instance */ - if (create[0] == 0x7 || create[0] == 0x10 || create[0] == 0x11) - continue; - - r = vcn_v4_0_limit_sched(p, job); - if (r) - goto out; - } - -out: - amdgpu_bo_kunmap(bo); - return r; -} - #define RADEON_VCN_ENGINE_TYPE_ENCODE (0x00000002) #define RADEON_VCN_ENGINE_TYPE_DECODE (0x00000003) #define RADEON_VCN_ENGINE_INFO (0x30000001) @@ -1960,7 +1859,8 @@ static int vcn_v4_0_ring_patch_cs_in_place(struct amdgpu_cs_parser *p, msg_buffer_addr = ((u64)amdgpu_ib_get_value(ib, idx + 7)) << 32 | amdgpu_ib_get_value(ib, idx + 8); - return vcn_v4_0_dec_msg(p, job, msg_buffer_addr); + return amdgpu_vcn_dec_msg_limit_sched(p, job, msg_buffer_addr, + vcn_v4_0_limit_sched); } else if (val == RADEON_VCN_ENGINE_TYPE_ENCODE) { sidx = vcn_v4_0_enc_find_ib_param(ib, RENCODE_IB_PARAM_SESSION_INIT, idx); if (sidx >= 0 && -- 2.53.0