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Mon, 13 Apr 2026 11:34:42 -0700 From: Amber Lin To: , CC: Amber Lin , Jonathan Kim Subject: [PATCH v4 04/10] drm/amdgpu: Create hqd info structure Date: Mon, 13 Apr 2026 14:34:20 -0400 Message-ID: <20260413183421.3191963-1-Amber.Lin@amd.com> X-Mailer: git-send-email 2.43.0 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: satlexmb08.amd.com (10.181.42.217) To satlexmb09.amd.com (10.181.42.218) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000EE3C:EE_|MN2PR12MB4389:EE_ X-MS-Office365-Filtering-Correlation-Id: 55df1728-1b3e-4368-14a7-08de998b553c X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|376014|1800799024|36860700016|82310400026|56012099003|18002099003; X-Microsoft-Antispam-Message-Info: CC2NjjJph5TnZ/pCT5FcFcpE9hpzeBXWTS8nPpqWNOIVxmWjeVzD8y71sr9CcpqRsTms/wVYLzn+EdIe2a4M1BZ5L3rCmXcw88BwTQ5Z/5Ligagpj8+XP0wVv3IVRwm0H7WvzfZ7FzeR7IlJ7Kzcwf3xWDuuz7aMqRuvro6PlcuKtuRiP4C1nQRArL/BBD9//RCbz4grj85twmVzOd/Trl43JU5f8Bobv52g4KlUZdKEzVVJcMDl+P8hWQ5fecSM8cbP/rNvY0Rx1d1lXJko2bCSbbXq2qlUDmaA41TAaYUcBshRhAUDQ6wCVhpnEAoUu2nlIsmunQY/LJ4LiiCCiiM4JTyX8RP7S1f5k3lf2CUkHc25Ww/gjtiSwubp7iaaoauzmVG3z8ZzNl0GIUnNNo1hnPuhtq0dHPqcFCrPUBbd5EQ+nkIO9xGJqhFRnEPWINVjSF4ij/CONjOODpgcYEWFEHHobtg58+9z2aAvuPJtcvm91DIf51+A9lc/DGyQnVdCXdih/u9JemSUgIlGvE+t8/0/dSqovBR+Kb3WjgRU1PVmR59CC+i+zNZcWS5GUBHjUpql1NznLiE6yEAnIKA+0yI2cy10KqYVBjFQTEExWvm9CqBq6w9HjQFz7+Xxa0rRll9+NMRVS6jjiXGQDWYxM3rdf/m1J45uBaMFn501aPKvnSVkACC4iGE9ETocDcolYdxQolA3L9aCIscoCi0yv5rv1CUXrXob6Oy7rS03Okje5H2nX3DyRo1TGBGmyKd1M678Wa4dcRQs3IVSKg== X-Forefront-Antispam-Report: CIP:165.204.84.17; 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Ip=[165.204.84.17]; Helo=[satlexmb08.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EE3C.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4389 X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" Create hung_queue_hqd_info structure and fill in hung queses information passed by MES, including queue type, pipe id, and queue id. Suggested-by: Jonathan Kim Signed-off-by: Amber Lin --- drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c | 13 ++++--------- drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h | 13 +++++++++++++ 2 files changed, 17 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c index f1f8bbfc31e0..ae42fbaba34f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c @@ -447,7 +447,7 @@ int amdgpu_mes_detect_and_reset_hung_queues(struct amdgpu_device *adev, { struct mes_detect_and_reset_queue_input input; u32 *db_array = adev->mes.hung_queue_db_array_cpu_addr[xcc_id]; - int r, i; + int hqd_info_offset = adev->mes.hung_queue_hqd_info_offset, r, i; if (!hung_db_num || !hung_db_array) return -EINVAL; @@ -481,18 +481,13 @@ int amdgpu_mes_detect_and_reset_hung_queues(struct amdgpu_device *adev, } } - if (r && !hung_db_num) { + if (r && !(*hung_db_num)) { dev_err(adev->dev, "Failed to detect and reset hung queues\n"); return r; } - /* - * TODO: return HQD info for MES scheduled user compute queue reset cases - * stored in hung_db_array hqd info offset to full array size - */ - - if (r) - dev_err(adev->dev, "failed to reset\n"); + for (i = hqd_info_offset; i < hqd_info_offset + *hung_db_num; i++) + hung_db_array[i] = db_array[i]; return r; } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h index f80e3aca9c78..2e6ae9f84db0 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h @@ -170,6 +170,19 @@ struct amdgpu_mes { uint64_t shared_cmd_buf_gpu_addr[AMDGPU_MAX_MES_INST_PIPES]; }; +struct amdgpu_mes_hung_queue_hqd_info { + union { + struct { + uint32_t queue_type: 3; // queue type + uint32_t pipe_index: 4; // pipe index + uint32_t queue_index: 8; // queue index + uint32_t reserved: 17; + }; + + uint32_t bit0_31; + }; +}; + struct amdgpu_mes_gang { int gang_id; int priority; -- 2.43.0