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Tue, 14 Apr 2026 03:59:51 -0500 From: Jesse Zhang To: CC: , Christian Koenig , Jesse Zhang , Jesse Zhang Subject: [PATCH v3 3/8] drm/amdgpu/gfx11: Fall back to pipe reset if per-queue reset ring test fails Date: Tue, 14 Apr 2026 16:58:50 +0800 Message-ID: <20260414085926.3171086-3-Jesse.Zhang@amd.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20260414085926.3171086-1-Jesse.Zhang@amd.com> References: <20260414085926.3171086-1-Jesse.Zhang@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF00002318:EE_|MW6PR12MB8899:EE_ X-MS-Office365-Filtering-Correlation-Id: 89dc6ca7-89f2-4e07-3f78-08de9a0434b6 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|376014|82310400026|36860700016|1800799024|18002099003|22082099003|56012099003; X-Microsoft-Antispam-Message-Info: vlYrcllrIkN9eIBvgbd8gyMb9HwRTga5AHyiEwmPg/iupRXdyZQtL3O6B6CgJI/1K5ZkcO1+AEiJzHlNowJhbycF/6V7DYsmJMGhZe7BpThpZTgvcgIrYjh5EJP/Trni+jq7dvpMzjAU0kg6jlsxtz956Trxxh6W20G7AFOP5AFbGrytHBFnR5JseZ6k80IszcglKZw1M9J7su1cO0z5e1hco0tzy7f4xappf+6P50tZm8TPOHbYdrZx7TuX05nqvwxZkb8R8l7Z/m6vH7o6NO3jMViGBZDHnWEyM7N2U5IXoEbw8HlMEtc9L0AvBmdwRSoy+BzrG6GPwPg5ZQlOC56wzaCq9jmMTEaZyxEx0IbX92BngGtafMkm2kClkn/bU6+GwSdAeFEcpemMA+7dgm3lXSnrHySPnpxHaqDY8rKfQSj6zOyXkXpsx4ZaFMmQt+RCNODl310sQubXSgrOzJTnMeL+FSJSGGRk2AetkSMxK6qAiHtAWipo9TAG7lPJB3VW2K7JbsekMxNlFAwj5PWlNKFqvj+t8e6SLmdBGR0UqLHvQxq/qtEa6He6dOnRCrBS9GPzZ/qELGWyg7mLzbNgoAHfYb0EYFjycgHg4HJLGFcikTFxZS41NH5folEOv01SG48eC00U7tFi1zX6Vod7BDVSCzF8qFuXaPTDfSfTqK21MooQCb56z+GJXctAaGYa768EXA1WNmz1eZX8L6jsdyDlWx5YYiM6J68zvCbeX39PMdgHHsm5aVCl+Qb0LUU0vQ30Ek7N46/b0zA80g== X-Forefront-Antispam-Report: CIP:165.204.84.17; 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Ip=[165.204.84.17]; Helo=[satlexmb08.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF00002318.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW6PR12MB8899 X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" After a per-queue reset via MES, verify that the queue is functional by performing a ring test. If the test fails, fall back to a full pipe reset to ensure proper recovery. This adds a fallback path similar to the one already present when the initial per-queue reset attempt fails, improving the robustness of KCQ reset handling on GFX11 hardware. Signed-off-by: Jesse Zhang --- drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c index e29e8e620699..fbef19ed46f9 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c @@ -7075,14 +7075,18 @@ static int gfx_v11_0_reset_kcq(struct amdgpu_ring *ring, struct amdgpu_fence *timedout_fence) { struct amdgpu_device *adev = ring->adev; + int reset_mode = AMDGPU_RESET_TYPE_PER_QUEUE; int r = 0; amdgpu_ring_reset_helper_begin(ring, timedout_fence); r = amdgpu_mes_reset_legacy_queue(ring->adev, ring, vmid, true, 0); + +pipe_reset: if (r) { dev_warn(adev->dev, "fail(%d) to reset kcq and try pipe reset\n", r); + reset_mode = AMDGPU_RESET_TYPE_PER_PIPE; amdgpu_amdkfd_suspend(adev, true); r = amdgpu_gfx_mec_pipe_reset_run(adev, ring->xcc_id, ring->me, ring->pipe, @@ -7105,6 +7109,13 @@ static int gfx_v11_0_reset_kcq(struct amdgpu_ring *ring, return r; } + if (reset_mode == AMDGPU_RESET_TYPE_PER_QUEUE) { + if (amdgpu_ring_reset_helper_end(ring, timedout_fence)) + goto pipe_reset; + else + return 0; + } + return amdgpu_ring_reset_helper_end(ring, timedout_fence); } -- 2.49.0