[PATCH] drm/amdgpu: allow unprivileged read of GC_THROTTLE_STATUS

[mjgajda@gmail.com]

From: "M. Gajda" <mjgajda@gmail.com>

GC_THROTTLE_STATUS is a read-only hardware status register present on all
RDNA GPU generations (GFX10/11/12).  It reports the state of the GFX
thermal throttle finite state machine:

  FSM_STATE    [3:0]  non-zero = GPU currently being throttled
  PATTERN_INDEX [9:4]  active throttle duty-cycle pattern

The register is never written by the driver.  No side-effects occur on
read.  Add it to the per-ASIC allowed_read_registers[] tables so that
unprivileged userspace can query it via the AMDGPU_INFO_READ_MMR_REG ioctl
(libdrm: amdgpu_read_mm_registers(3)).

This enables monitoring tools such as radeontop to display GPU thermal
throttle status without root privileges -- information of the same
sensitivity class as GPU temperature, which is already exposed via the
AMDGPU_INFO_SENSOR_GPU_TEMP sensor ioctl.

Register offsets per generation:
  GFX10 (RDNA 1/2): mmGC_THROTTLE_STATUS  0x2032  BASE_IDX 0
  GFX11 (RDNA 3):  regGC_THROTTLE_STATUS  0x1b0a  BASE_IDX 1
  GFX12 (RDNA 4):  regGC_THROTTLE_STATUS  0x1b1c  BASE_IDX 1

Source: drivers/gpu/drm/amd/include/asic_reg/gc/
  gc_10_3_0_{offset,sh_mask}.h, gc_11_0_0_{offset,sh_mask}.h,
  gc_12_0_0_{offset,sh_mask}.h

Public ISA documentation:
  RDNA 1: https://developer.amd.com/wp-content/resources/RDNA_Shader_ISA.pdf
  RDNA 2: https://www.amd.com/content/dam/amd/en/documents/radeon-tech-docs/instruction-set-architectures/rdna2-shader-instruction-set-architecture.pdf
  RDNA 3: https://docs.amd.com/v/u/en-US/rdna3-shader-instruction-set-architecture
  RDNA 4: https://docs.amd.com/v/u/en-US/rdna4-instruction-set-architecture

Signed-off-by: M. Gajda <mjgajda@gmail.com>
---
 drivers/gpu/drm/amd/amdgpu/nv.c    | 6 ++++++
 drivers/gpu/drm/amd/amdgpu/soc21.c | 6 ++++++
 drivers/gpu/drm/amd/amdgpu/soc24.c | 6 ++++++
 3 files changed, 18 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
index 7ce1a1b95..80594c793 100644
--- a/drivers/gpu/drm/amd/amdgpu/nv.c
+++ b/drivers/gpu/drm/amd/amdgpu/nv.c
@@ -352,6 +352,12 @@ static struct soc15_allowed_register_entry nv_allowed_read_registers[] = {
 	{ SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STALLED_STAT1)},
 	{ SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STATUS)},
 	{ SOC15_REG_ENTRY(GC, 0, mmGB_ADDR_CONFIG)},
+	/*
+	 * GC_THROTTLE_STATUS (offset 0x2032): read-only thermal throttle FSM.
+	 * FSM_STATE [3:0] != 0 indicates the GPU is currently being throttled.
+	 * Defined in gc_10_3_0_offset.h / gc_10_3_0_sh_mask.h
+	 */
+	{ SOC15_REG_ENTRY(GC, 0, mmGC_THROTTLE_STATUS)},
 };
 
 static uint32_t nv_read_indexed_register(struct amdgpu_device *adev, u32 se_num,
diff --git a/drivers/gpu/drm/amd/amdgpu/soc21.c b/drivers/gpu/drm/amd/amdgpu/soc21.c
index fbd1d97f3..8c2472bd0 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc21.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc21.c
@@ -304,6 +304,12 @@ static struct soc15_allowed_register_entry soc21_allowed_read_registers[] = {
 	{ SOC15_REG_ENTRY(GC, 0, regCP_CPC_STALLED_STAT1)},
 	{ SOC15_REG_ENTRY(GC, 0, regCP_CPC_STATUS)},
 	{ SOC15_REG_ENTRY(GC, 0, regGB_ADDR_CONFIG)},
+	/*
+	 * GC_THROTTLE_STATUS (offset 0x1b0a): read-only thermal throttle FSM.
+	 * FSM_STATE [3:0] != 0 indicates the GPU is currently being throttled.
+	 * Defined in gc_11_0_0_offset.h / gc_11_0_0_sh_mask.h
+	 */
+	{ SOC15_REG_ENTRY(GC, 0, regGC_THROTTLE_STATUS)},
 };
 
 static uint32_t soc21_read_indexed_register(struct amdgpu_device *adev, u32 se_num,
diff --git a/drivers/gpu/drm/amd/amdgpu/soc24.c b/drivers/gpu/drm/amd/amdgpu/soc24.c
index d1adf19a5..617ee0a4d 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc24.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc24.c
@@ -130,6 +130,12 @@ static struct soc15_allowed_register_entry soc24_allowed_read_registers[] = {
 	{ SOC15_REG_ENTRY(GC, 0, regCP_CPC_STALLED_STAT1)},
 	{ SOC15_REG_ENTRY(GC, 0, regCP_CPC_STATUS)},
 	{ SOC15_REG_ENTRY(GC, 0, regGB_ADDR_CONFIG)},
+	/*
+	 * GC_THROTTLE_STATUS (offset 0x1b1c): read-only thermal throttle FSM.
+	 * FSM_STATE [3:0] != 0 indicates the GPU is currently being throttled.
+	 * Defined in gc_12_0_0_offset.h / gc_12_0_0_sh_mask.h
+	 */
+	{ SOC15_REG_ENTRY(GC, 0, regGC_THROTTLE_STATUS)},
 };
 
 static uint32_t soc24_read_indexed_register(struct amdgpu_device *adev,
-- 
2.51.0