[PATCH 7/7] drm/amdgpu/vce1: Align VCPU BO GART address to nearest power of two

["Timur Kristóf" <timur.kristof@gmail.com>]

VCE accesses memory, including its firmware, through a BAR.
It works slightly differently on each generation.
In case of VCE1, the start address of this BAR is zero
and we can't change it due to the firmware validation mechanism.

Align the GART address of the VCPU BO like the VRAM address,
in order to prevent it from crossing the boundaries of its BAR.

This fixes VCE1 initialization failure after suspend/resume.

Fixes: 66a80158aa2a ("amdgpu/vce: use amdgpu_gtt_mgr_alloc_entries")
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
---
 drivers/gpu/drm/amd/amdgpu/vce_v1_0.c | 11 +++++++++--
 1 file changed, 9 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v1_0.c
index 100aa48204c77..9ddd635449873 100644
--- a/drivers/gpu/drm/amd/amdgpu/vce_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vce_v1_0.c
@@ -527,11 +527,17 @@ static int vce_v1_0_early_init(struct amdgpu_ip_block *ip_block)
  * To accomodate that, we put GART to the LOW address range
  * and reserve some GART pages where we map the VCPU BO,
  * so that it gets a 32-bit address.
+ *
+ * VCE accesses memory, including its firmware, through a BAR.
+ * It works slightly differently on each generation.
+ * In case of VCE1, the start address of this BAR is zero
+ * and we can't change it due to the firmware validation mechanism.
  */
 static int vce_v1_0_ensure_vcpu_bo_32bit_addr(struct amdgpu_device *adev)
 {
 	u64 bo_size = amdgpu_bo_size(adev->vce.vcpu_bo);
-	u64 max_vcpu_bo_addr = 0x0fffffff - bo_size;
+	u64 aligned_size = roundup_pow_of_two(bo_size);
+	u64 max_vcpu_bo_addr = 0x0fffffff - aligned_size;
 	u64 num_pages = ALIGN(bo_size, AMDGPU_GPU_PAGE_SIZE) / AMDGPU_GPU_PAGE_SIZE;
 	u64 pa = amdgpu_gmc_vram_pa(adev, adev->vce.vcpu_bo);
 	u64 flags = AMDGPU_PTE_READABLE | AMDGPU_PTE_WRITEABLE | AMDGPU_PTE_VALID;
@@ -543,7 +549,8 @@ static int vce_v1_0_ensure_vcpu_bo_32bit_addr(struct amdgpu_device *adev)
 
 	if (!drm_mm_node_allocated(&adev->vce.gart_node)) {
 		r = amdgpu_gtt_mgr_alloc_entries(&adev->mman.gtt_mgr,
-						 &adev->vce.gart_node, num_pages, 0,
+						 &adev->vce.gart_node, num_pages,
+						 aligned_size >> AMDGPU_GPU_PAGE_SHIFT,
 						 DRM_MM_INSERT_LOW);
 		if (r)
 			return r;
-- 
2.53.0