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Fri, 24 Apr 2026 03:20:09 -0500 Received: from JesseDEV.amd.com (10.180.168.240) by satlexmb07.amd.com (10.181.42.216) with Microsoft SMTP Server id 15.2.2562.17 via Frontend Transport; Fri, 24 Apr 2026 03:20:03 -0500 From: Jesse Zhang To: CC: , Christian Koenig , Jesse.zhang , Jesse Zhang Subject: [PATCH 02/10] drm/amdgpu/userq: route SDMA UMQ doorbells through the kernel pool Date: Fri, 24 Apr 2026 16:18:47 +0800 Message-ID: <20260424081955.873090-2-Jesse.Zhang@amd.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20260424081955.873090-1-Jesse.Zhang@amd.com> References: <20260424081955.873090-1-Jesse.Zhang@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MN1PEPF0000F0DF:EE_|DS3PR12MB999218:EE_ X-MS-Office365-Filtering-Correlation-Id: cca2fe30-0d20-45ae-f13e-08dea1da4e77 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|36860700016|376014|82310400026|1800799024|22082099003|18002099003|56012099003; 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DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: VReyaDxYJ/lI/op50EnIJ5GokPgJ8X8kcER6GT3WeRi78TQwp+n+XM4B+EC12mjESxzhM/pXqthM3QRaeBhnTSEBb10csRUarHoLi5JRFl0qs1WvZbzz3YGgRtoBIhgjsQvmXkDgEjsnclw9BQpj9sBVwfmUp8g7flJIuQA3Uk5GLzRNwdnHYS2BWnHmhGUYmVtyczltXhGeRpH0ElaawdYxJVVAR0gEv2SGq5cdccBcUK7tqLSoL1bCxIgy1BbmACzKVbjR5tOcS3ac98NIabYSVfcjrNZamsFbaGGkTUYIiPzEYlATmwNqb1GDOZxrigyQIcQN2tn5MjCv6odhNyDSP7/Od03XBHtl3XcxeixZknoz9CG84L9EosfwRYlAbywAiYur7/vD3NVfskop/kCRbvMTGRwsCsy3vyrJ3GZdy2EihKS3o1uQlO25ukSG X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 Apr 2026 08:20:12.4262 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: cca2fe30-0d20-45ae-f13e-08dea1da4e77 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: MN1PEPF0000F0DF.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS3PR12MB999218 X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" From: "Jesse.zhang" User-allocated DOORBELL BOs land at BAR offsets outside the firmware-managed NBIO SDMA decode window and cannot reach the SDMA back-end. For AMDGPU_HW_IP_DMA queues, ignore the user-supplied doorbell index and allocate one from the per-device pool added in the previous patch. Track the assigned slot id on the queue so it can be returned to the bitmap on destroy. Add a new sdma_doorbell_offset_bytes field to drm_amdgpu_userq_out that tells userspace where its kernel-allocated qword slot lives inside the BO it will mmap (the BO handle comes from the AMDGPU_INFO_SDMA_USERQ_DOORBELL ioctl added later in the series). Signed-off-by: Jesse Zhang --- drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c | 47 +++++++++++++++++++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_userq.h | 7 ++++ include/uapi/drm/amdgpu_drm.h | 8 ++++ 3 files changed, 62 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c index 8f48520cb822..cea0f9cb59d0 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c @@ -662,6 +662,10 @@ amdgpu_userq_destroy(struct amdgpu_userq_mgr *uq_mgr, struct amdgpu_usermode_que amdgpu_bo_unpin(queue->wptr_obj.obj); amdgpu_bo_unreserve(queue->wptr_obj.obj); amdgpu_bo_unref(&queue->wptr_obj.obj); + + if (queue->sdma_userq_db_slot >= 0) + amdgpu_sdma_userq_doorbell_free(adev, + (u32)queue->sdma_userq_db_slot); kfree(queue); pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); @@ -762,6 +766,7 @@ amdgpu_userq_create(struct drm_file *filp, union drm_amdgpu_userq *args) queue->queue_type = args->in.ip_type; queue->vm = &fpriv->vm; queue->priority = priority; + queue->sdma_userq_db_slot = -1; db_info.queue_type = queue->queue_type; db_info.doorbell_handle = queue->doorbell_handle; @@ -792,6 +797,38 @@ amdgpu_userq_create(struct drm_file *filp, union drm_amdgpu_userq *args) goto clean_mapping; } + /* + * SDMA UMQ doorbell override: user-allocated DOORBELL BOs land at + * BAR offsets outside the firmware-managed NBIO SDMA decode window + * and cannot reach the SDMA back-end. Replace the user-supplied + * doorbell index with one allocated from the per-device + * sdma.userq_db_obj BO that sits inside the routable window. + * Userspace fetches a GEM handle for that BO via + * AMDGPU_INFO_SDMA_USERQ_DOORBELL and mmap()s it through the + * standard GEM_MMAP path; sdma_doorbell_offset_bytes (returned in + * args->out) tells userspace where inside that mapping its slot + * lives. + */ + if (queue->queue_type == AMDGPU_HW_IP_DMA && + adev->sdma.userq_db_obj) { + u32 slot_id; + + r = amdgpu_sdma_userq_doorbell_alloc(adev, &slot_id); + if (r) { + drm_file_err(uq_mgr->file, + "SDMA UMQ doorbell pool exhausted (err=%d)\n", + r); + goto clean_mapping; + } + /* + * Slot id is a qword index inside the routable window; + * convert to absolute BAR dword index. + */ + index = (u64)(adev->doorbell_index.sdma_engine[0] << 1) + + (u64)slot_id * 2; + queue->sdma_userq_db_slot = (int)slot_id; + } + queue->doorbell_index = index; xa_init_flags(&queue->fence_drv_xa, XA_FLAGS_ALLOC); r = amdgpu_userq_fence_driver_alloc(adev, &queue->fence_drv); @@ -851,6 +888,16 @@ amdgpu_userq_create(struct drm_file *filp, union drm_amdgpu_userq *args) amdgpu_userq_init_hang_detect_work(queue); args->out.queue_id = qid; + if (queue->sdma_userq_db_slot >= 0) { + /* + * Tell userspace where inside its mmap of the SDMA UMQ + * doorbell BO (handle returned by + * AMDGPU_INFO_SDMA_USERQ_DOORBELL) the assigned qword slot + * lives. + */ + args->out.sdma_doorbell_offset_bytes = + (u64)queue->sdma_userq_db_slot * sizeof(u64); + } atomic_inc(&uq_mgr->userq_count[queue->queue_type]); mutex_unlock(&uq_mgr->userq_mutex); return 0; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.h index 675fe6395ac8..cdfced627dec 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.h @@ -59,6 +59,13 @@ struct amdgpu_usermode_queue { uint64_t doorbell_handle; uint64_t doorbell_index; uint64_t flags; + /* + * For SDMA UMQs whose doorbell came from the kernel-managed pool + * (amdgpu_sdma_userq_doorbell_alloc), record the slot id so it can + * be returned to the bitmap on queue destroy. -1 means the queue + * is using a user-supplied doorbell BO. + */ + int sdma_userq_db_slot; struct amdgpu_mqd_prop *userq_prop; struct amdgpu_userq_mgr *userq_mgr; struct amdgpu_vm *vm; diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h index 9f3090db2f16..79e8bbda046b 100644 --- a/include/uapi/drm/amdgpu_drm.h +++ b/include/uapi/drm/amdgpu_drm.h @@ -421,6 +421,14 @@ struct drm_amdgpu_userq_out { */ __u32 queue_id; __u32 _pad; + /** + * For SDMA usermode queues whose doorbell was assigned by the + * kernel from the per-device pool (see AMDGPU_INFO_SDMA_USERQ_DOORBELL), + * this field carries the byte offset of the assigned slot inside + * the routable doorbell window so userspace can write there. + * 0 means the kernel did not override the user's doorbell. + */ + __u64 sdma_doorbell_offset_bytes; }; union drm_amdgpu_userq { -- 2.49.0