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Fri, 24 Apr 2026 03:20:56 -0500 Received: from JesseDEV.amd.com (10.180.168.240) by satlexmb07.amd.com (10.181.42.216) with Microsoft SMTP Server id 15.2.2562.17 via Frontend Transport; Fri, 24 Apr 2026 03:20:50 -0500 From: Jesse Zhang To: CC: , Christian Koenig , Jesse.zhang , Jesse Zhang Subject: [PATCH 09/10] drm/amdgpu/mes_userqueue: mark SDMA UMQs as user-mode submission Date: Fri, 24 Apr 2026 16:18:54 +0800 Message-ID: <20260424081955.873090-9-Jesse.Zhang@amd.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20260424081955.873090-1-Jesse.Zhang@amd.com> References: <20260424081955.873090-1-Jesse.Zhang@amd.com> MIME-Version: 1.0 Content-Type: text/plain; charset="Y" Content-Transfer-Encoding: 8bit X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF0000231E:EE_|IA1PR12MB6284:EE_ X-MS-Office365-Filtering-Correlation-Id: c8026443-1d3a-4eab-6837-08dea1da697b X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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Ip=[165.204.84.17]; Helo=[satlexmb08.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF0000231E.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB6284 X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" From: "Jesse.zhang" For AMDGPU_HW_IP_DMA queues, set mes_add_queue_input.is_user_mode_submission and a stable unmap_flag_addr (a kernel-owned dword in the MQD object's tail padding). This tells MES to use the new wptr_mc / unmap_flag scheme so the PROTECTED_FENCE at the tail of every SDMA IB no longer terminates the queue. Combined with the NOTIFY_WORK_ON_UNMAPPED_QUEUE wakeup added in a follow-up patch, this lets multi-IB submissions on a single SDMA UMQ work end-to-end. Signed-off-by: Jesse Zhang --- drivers/gpu/drm/amd/amdgpu/mes_userqueue.c | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/mes_userqueue.c b/drivers/gpu/drm/amd/amdgpu/mes_userqueue.c index d12cd1b7790b..3dbcddb46b24 100644 --- a/drivers/gpu/drm/amd/amdgpu/mes_userqueue.c +++ b/drivers/gpu/drm/amd/amdgpu/mes_userqueue.c @@ -165,6 +165,28 @@ static int mes_userq_map(struct amdgpu_usermode_queue *queue) queue_input.doorbell_offset = userq_props->doorbell_index; queue_input.page_table_base_addr = amdgpu_gmc_pd_addr(queue->vm->root.bo); queue_input.wptr_mc_addr = queue->wptr_obj.gpu_addr; + /* + * SDMA UMQs need is_user_mode_submission so MES treats them as user + * queues (using the new wptr_mc_addr / unmap_flag_addr scheme). + * Without this MES uses end-of-MQD for unmap_flag, sees PROTECTED_FENCE + * as a "queue done" signal, and gangs the queue out forever. Combined + * with NOTIFY_WORK_ON_UNMAPPED_QUEUE poke from amdgpu_userq_signal_ioctl + * this lets multi-IB submissions work. Use queue->mqd.gpu_addr + + * mqd_size as a stable kernel-owned location for unmap_flag — userspace + * never reads it; the kernel just needs SOMETHING valid to give MES. + */ + if (queue->queue_type == AMDGPU_HW_IP_DMA) { + queue_input.is_user_mode_submission = 1; + /* + * Same offset MES would derive in legacy mode + * (get_unmap_flag_addr_from_end_of_mqd in MES src 12). Lives + * inside the allocated MQD object's tail padding so it's a + * valid MC address; the kernel never reads it back — its only + * purpose is to keep MES happy. + */ + queue_input.unmap_flag_addr = queue->mqd.gpu_addr + + adev->mqds[queue->queue_type].mqd_size + sizeof(u32); + } amdgpu_mes_lock(&adev->mes); r = adev->mes.funcs->add_hw_queue(&adev->mes, &queue_input); -- 2.49.0