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Mon, 27 Apr 2026 01:36:48 -0700 Received: from JesseDEV.amd.com (10.180.168.240) by satlexmb08.amd.com (10.181.42.217) with Microsoft SMTP Server id 15.2.2562.17 via Frontend Transport; Mon, 27 Apr 2026 03:36:42 -0500 From: Jesse Zhang To: CC: , Christian Koenig , Jesse.zhang , Jesse Zhang Subject: [PATCH v2 11/11] drm/amdgpu/userq_fence: wake gangs-out SDMA UMQs via NOTIFY Date: Mon, 27 Apr 2026 16:34:37 +0800 Message-ID: <20260427083543.1328533-11-Jesse.Zhang@amd.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20260427083543.1328533-1-Jesse.Zhang@amd.com> References: <20260427083543.1328533-1-Jesse.Zhang@amd.com> MIME-Version: 1.0 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 8bit X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH1PEPF0000A345:EE_|LV3PR12MB9331:EE_ X-MS-Office365-Filtering-Correlation-Id: 71baac88-e1f7-45b8-1317-08dea4381fc8 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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Ip=[165.204.84.17]; Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH1PEPF0000A345.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV3PR12MB9331 X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" From: "Jesse.zhang" SDMA has no CP_UNMAPPED_DOORBELL HW intercept, so once MES gangs the queue out (after the first IB idles it) per-queue doorbell rings from userspace hit a mapped-out HW slot and are silently dropped: rptr stops advancing and FENCE IRQ never fires. After the SDMA UMQ's first IB has actually completed (fence_drv->cpu_addr != 0), issue MES_MISC_OP_NOTIFY_WORK_ON_UNMAPPED_QUEUE and ring the priority's aggregated doorbell so MES re-evaluates scheduling and re-maps the queue for the next IB. The first submission is intentionally skipped — the queue is still mapped from MAP_QUEUE then, and an extra notify would race the initial scheduling. Signed-off-by: Jesse Zhang --- .../gpu/drm/amd/amdgpu/amdgpu_userq_fence.c | 33 +++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c index a58342c2ac44..6ef4cbd5d5da 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c @@ -598,6 +598,39 @@ int amdgpu_userq_signal_ioctl(struct drm_device *dev, void *data, /* drop the reference acquired in fence creation function */ dma_fence_put(fence); + /* + * SDMA UMQ wake: SDMA has no CP_UNMAPPED_DOORBELL HW intercept, so + * once MES gangs the queue out (after the first IB's PROTECTED_FENCE + * idles the queue), subsequent per-queue doorbell rings hit a + * mapped-out HW slot and are silently ignored — rptr stops + * advancing, FENCE IRQ never fires. The MES MISC API + * NOTIFY_WORK_ON_UNMAPPED_QUEUE flips MES's hasReadyQueues flag for + * the queue's priority level, which makes MES re-evaluate + * scheduling and re-map our SDMA UMQ for the next IB. + * + * Skip on the very first submission (fence_drv->cpu_addr == 0 + * means SDMA hasn't completed any IB yet, so MES still has the + * queue mapped from MAP_QUEUE — calling NOTIFY here would race the + * initial scheduling and starve the first IB). + */ + if (queue && queue->queue_type == AMDGPU_HW_IP_DMA && + adev->enable_mes && adev->mes.funcs->misc_op && + queue->fence_drv && queue->fence_drv->cpu_addr && + le64_to_cpu(*queue->fence_drv->cpu_addr) != 0) { + struct mes_misc_op_input op = { 0 }; + u32 agg_db = adev->mes.aggregated_doorbells[ + AMDGPU_MES_PRIORITY_LEVEL_NORMAL]; + + op.op = MES_MISC_OP_NOTIFY_WORK_ON_UNMAPPED_QUEUE; + op.notify_work.priority_level = AMDGPU_MES_PRIORITY_LEVEL_NORMAL; + amdgpu_mes_lock(&adev->mes); + (void)adev->mes.funcs->misc_op(&adev->mes, &op); + amdgpu_mes_unlock(&adev->mes); + + if (agg_db) + WDOORBELL64(agg_db, queue->doorbell_index); + } + exec_fini: drm_exec_fini(&exec); put_gobj_write: -- 2.49.0