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[84.0.18.144]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-45da0fe0fecsm41028224f8f.26.2026.05.19.03.21.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 May 2026 03:21:22 -0700 (PDT) From: =?UTF-8?q?Timur=20Krist=C3=B3f?= To: amd-gfx@lists.freedesktop.org, Alex Deucher , christian.koenig@amd.com, Natalie Vock , Melissa Wen , Harry Wentland , Alex Hung , Roman Li , Leo Li , Mario Limonciello Cc: =?UTF-8?q?Timur=20Krist=C3=B3f?= Subject: [PATCH 02/14] drm/amd/display: Delete dce_get_required_clocks_state() Date: Tue, 19 May 2026 12:21:06 +0200 Message-ID: <20260519102118.246466-3-timur.kristof@gmail.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260519102118.246466-1-timur.kristof@gmail.com> References: <20260519102118.246466-1-timur.kristof@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" It is not called from anywhere anymore. Signed-off-by: Timur Kristóf Reviewed-by: Melissa Wen --- .../display/dc/clk_mgr/dce100/dce_clk_mgr.c | 34 ------------------- .../display/dc/clk_mgr/dce100/dce_clk_mgr.h | 3 -- 2 files changed, 37 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c index 4ccc6c742d00..e8daee975b79 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c @@ -220,40 +220,6 @@ uint32_t dce_get_max_pixel_clock_for_all_paths(struct dc_state *context) return max_pix_clk; } -enum dm_pp_clocks_state dce_get_required_clocks_state( - struct clk_mgr *clk_mgr_base, - struct dc_state *context) -{ - struct clk_mgr_internal *clk_mgr_dce = TO_CLK_MGR_INTERNAL(clk_mgr_base); - int i; - enum dm_pp_clocks_state low_req_clk; - int max_pix_clk = dce_get_max_pixel_clock_for_all_paths(context); - - /* Iterate from highest supported to lowest valid state, and update - * lowest RequiredState with the lowest state that satisfies - * all required clocks - */ - for (i = clk_mgr_dce->max_clks_state; i >= DM_PP_CLOCKS_STATE_ULTRA_LOW; i--) - if (context->bw_ctx.bw.dce.dispclk_khz > - clk_mgr_dce->max_clks_by_state[i].display_clk_khz - || max_pix_clk > - clk_mgr_dce->max_clks_by_state[i].pixel_clk_khz) - break; - - low_req_clk = i + 1; - if (low_req_clk > clk_mgr_dce->max_clks_state) { - /* set max clock state for high phyclock, invalid on exceeding display clock */ - if (clk_mgr_dce->max_clks_by_state[clk_mgr_dce->max_clks_state].display_clk_khz - < context->bw_ctx.bw.dce.dispclk_khz) - low_req_clk = DM_PP_CLOCKS_STATE_INVALID; - else - low_req_clk = clk_mgr_dce->max_clks_state; - } - - return low_req_clk; -} - - /* TODO: remove use the two broken down functions */ int dce_set_clock( struct clk_mgr *clk_mgr_base, diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.h b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.h index 9ea1b0a9923d..e1c6a92d7957 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.h +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.h @@ -32,9 +32,6 @@ /* functions shared by other dce clk mgrs */ int dce_adjust_dp_ref_freq_for_ss(struct clk_mgr_internal *clk_mgr_dce, int dp_ref_clk_khz); int dce_get_dp_ref_freq_khz(struct clk_mgr *clk_mgr_base); -enum dm_pp_clocks_state dce_get_required_clocks_state( - struct clk_mgr *clk_mgr_base, - struct dc_state *context); uint32_t dce_get_max_pixel_clock_for_all_paths(struct dc_state *context); -- 2.54.0