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Tue, 11 Aug 2026 10:49:32 -0500 From: James Lin To: CC: Harry Wentland , Leo Li , Aurabindo Pillai , Roman Li , Wayne Lin , Tom Chung , "Fangzhi Zuo" , Dan Wheeler , Ray Wu , Ivan Lipski , Alex Hung , James Lin , Chenyu Chen , Tomasz Siemek , Alvin Lee , James Lin Subject: [PATCH 10/24] drm/amd/display: Refactor HUBP_WAIT_FOR_DCC_META_PROP to drop pipe_ctx Date: Tue, 11 Aug 2026 05:28:44 +0800 Message-ID: <20260810213010.1703162-11-PingLei.Lin@amd.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260810213010.1703162-1-PingLei.Lin@amd.com> References: <20260810213010.1703162-1-PingLei.Lin@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN2PEPF00004FBB:EE_|SJ0PR12MB7066:EE_ X-MS-Office365-Filtering-Correlation-Id: 5b6b63bd-bdb4-47ac-f88f-08def7c02881 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|82310400026|1800799024|376014|36860700016|23010399003|10067099003|56012099006|11063799006|6133799003|18002099003|22082099003; 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[how] Precalculate delay during building stage instead during execution. Reviewed-by: Alvin Lee Signed-off-by: Tomasz Siemek Signed-off-by: James Lin --- drivers/gpu/drm/amd/display/dc/core/dc.c | 4 +- .../drm/amd/display/dc/core/dc_hw_sequencer.c | 47 +++++++++++-------- .../amd/display/dc/hwss/dcn401/dcn401_hwseq.c | 24 ++-------- .../amd/display/dc/hwss/dcn401/dcn401_hwseq.h | 3 +- .../drm/amd/display/dc/hwss/hw_sequencer.h | 11 ++--- 5 files changed, 36 insertions(+), 53 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index bc2207d29954..6f7b715d4717 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -4967,9 +4967,7 @@ static void commit_planes_for_stream(struct dc *dc, top_pipe_to_program->stream_res.tg); } - if (dc->hwss.wait_for_dcc_meta_propagation) { - dc->hwss.wait_for_dcc_meta_propagation(dc, top_pipe_to_program); - } + hwss_hubp_wait_for_dcc_meta_prop(dc, top_pipe_to_program); if (dc->hwseq->funcs.wait_for_pipe_update_if_needed) dc->hwseq->funcs.wait_for_pipe_update_if_needed(dc, top_pipe_to_program, update_type < UPDATE_TYPE_FULL); diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c index bfb598a22c26..a8ff59f619c5 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c @@ -1142,6 +1142,22 @@ void hwss_build_post_unlock_full_sequence(struct dc *dc, } } +static uint32_t get_dcc_meta_propagation_delay(struct dc *dc, struct pipe_ctx *pipe_ctx) +{ + /* check if any surfaces are updating address while using flip immediate and dcc */ + while (pipe_ctx != NULL) { + if (pipe_ctx->plane_state && + pipe_ctx->plane_state->dcc.enable && + pipe_ctx->plane_state->flip_immediate && + pipe_ctx->plane_state->update_bits.addr_update) { + return dc->debug.dcc_meta_propagation_delay_us; + } + /* check next pipe */ + pipe_ctx = pipe_ctx->bottom_pipe; + } + return 0; +} + void hwss_build_fast_sequence(struct dc *dc, struct dc_dmub_cmd *dc_dmub_cmd, unsigned int dmub_cmd_count, @@ -1165,8 +1181,7 @@ void hwss_build_fast_sequence(struct dc *dc, return; if (dc->hwss.wait_for_dcc_meta_propagation) { - block_sequence[*num_steps].params.wait_for_dcc_meta_propagation_params.dc = dc; - block_sequence[*num_steps].params.wait_for_dcc_meta_propagation_params.top_pipe_to_program = pipe_ctx; + block_sequence[*num_steps].params.wait_for_dcc_meta_propagation_params.delay = get_dcc_meta_propagation_delay(dc, pipe_ctx); block_sequence[*num_steps].func = HUBP_WAIT_FOR_DCC_META_PROP; (*num_steps)++; } @@ -1756,9 +1771,7 @@ void hwss_execute_sequence(struct dc *dc, hwss_subvp_save_surf_addr(params); break; case HUBP_WAIT_FOR_DCC_META_PROP: - dc->hwss.wait_for_dcc_meta_propagation( - params->wait_for_dcc_meta_propagation_params.dc, - params->wait_for_dcc_meta_propagation_params.top_pipe_to_program); + dc->hwss.wait_for_dcc_meta_propagation(params->wait_for_dcc_meta_propagation_params.delay); break; case DMUB_HW_CONTROL_LOCK_FAST: dc->hwss.dmub_hw_control_lock_fast(params); @@ -2471,21 +2484,6 @@ void hwss_add_dmub_subvp_save_surf_addr(struct block_sequence_state *seq_state, } } -/* - * Helper function to add HUBP wait for DCC meta propagation to block sequence - */ -void hwss_add_hubp_wait_for_dcc_meta_prop(struct block_sequence_state *seq_state, - struct dc *dc, - struct pipe_ctx *top_pipe_to_program) -{ - if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { - seq_state->steps[*seq_state->num_steps].params.wait_for_dcc_meta_propagation_params.dc = dc; - seq_state->steps[*seq_state->num_steps].params.wait_for_dcc_meta_propagation_params.top_pipe_to_program = top_pipe_to_program; - seq_state->steps[*seq_state->num_steps].func = HUBP_WAIT_FOR_DCC_META_PROP; - (*seq_state->num_steps)++; - } -} - /* * Helper function to add HUBP wait pipe read start to block sequence */ @@ -6189,3 +6187,12 @@ void get_refresh_rate_confirm_color(struct pipe_ctx *pipe_ctx, struct tg_color * pipe_ctx->visual_confirm_color.color_b_cb = (uint16_t)color_value; } } + +void hwss_hubp_wait_for_dcc_meta_prop(struct dc *dc, struct pipe_ctx *top_pipe_to_program) +{ + if (dc->hwss.wait_for_dcc_meta_propagation) { + uint32_t delay = get_dcc_meta_propagation_delay(dc, top_pipe_to_program); + dc->hwss.wait_for_dcc_meta_propagation(delay); + } +} + diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c index f20a7b99d20c..42b2fbb8a4ae 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c @@ -1333,28 +1333,10 @@ bool dcn401_apply_idle_power_optimizations(struct dc *dc, bool enable) return true; } -void dcn401_wait_for_dcc_meta_propagation(const struct dc *dc, - const struct pipe_ctx *top_pipe) +void dcn401_wait_for_dcc_meta_propagation(uint32_t delay) { - bool is_wait_needed = false; - const struct pipe_ctx *pipe_ctx = top_pipe; - - /* check if any surfaces are updating address while using flip immediate and dcc */ - while (pipe_ctx != NULL) { - if (pipe_ctx->plane_state && - pipe_ctx->plane_state->dcc.enable && - pipe_ctx->plane_state->flip_immediate && - pipe_ctx->plane_state->update_bits.addr_update) { - is_wait_needed = true; - break; - } - - /* check next pipe */ - pipe_ctx = pipe_ctx->bottom_pipe; - } - - if (is_wait_needed && dc->debug.dcc_meta_propagation_delay_us > 0) { - udelay(dc->debug.dcc_meta_propagation_delay_us); + if (delay > 0) { + udelay(delay); } } diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h index 69c7dc73a29a..2e3392c963d0 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h @@ -57,8 +57,7 @@ void dcn401_set_cursor_position(struct pipe_ctx *pipe_ctx); bool dcn401_apply_idle_power_optimizations(struct dc *dc, bool enable); -void dcn401_wait_for_dcc_meta_propagation(const struct dc *dc, - const struct pipe_ctx *top_pipe_to_program); +void dcn401_wait_for_dcc_meta_propagation(uint32_t delay); void dcn401_prepare_bandwidth(struct dc *dc, struct dc_state *context); diff --git a/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h index 129120ac6d9e..bf63281a8cd2 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h +++ b/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h @@ -182,8 +182,7 @@ struct subvp_save_surf_addr { }; struct wait_for_dcc_meta_propagation_params { - const struct dc *dc; - const struct pipe_ctx *top_pipe_to_program; + uint32_t delay; }; struct dmub_hw_control_lock_fast_params { @@ -1654,8 +1653,7 @@ struct hw_sequencer_funcs { bool (*is_pipe_topology_transition_seamless)(struct dc *dc, const struct dc_state *cur_ctx, const struct dc_state *new_ctx); - void (*wait_for_dcc_meta_propagation)(const struct dc *dc, - const struct pipe_ctx *top_pipe_to_program); + void (*wait_for_dcc_meta_propagation)(uint32_t delay); void (*dmub_hw_control_lock)(struct dc *dc, struct dc_state *context, bool lock); @@ -2119,6 +2117,8 @@ void hwss_setup_periodic_interrupt(struct dc *dc, struct pipe_ctx *pipe_ctx); void hwss_disable_audio_stream(struct dc *dc, union block_sequence_params *params); +void hwss_hubp_wait_for_dcc_meta_prop(struct dc *dc, struct pipe_ctx *top_pipe_to_program); + void hwss_add_optc_pipe_control_lock(struct block_sequence_state *seq_state, struct dc *dc, struct pipe_ctx *pipe_ctx, bool lock); @@ -2166,9 +2166,6 @@ void hwss_add_dmub_send_dmcub_cmd(struct block_sequence_state *seq_state, void hwss_add_dmub_subvp_save_surf_addr(struct block_sequence_state *seq_state, struct dc_dmub_srv *dc_dmub_srv, struct dc_plane_address *addr, uint8_t subvp_index); -void hwss_add_hubp_wait_for_dcc_meta_prop(struct block_sequence_state *seq_state, - struct dc *dc, struct pipe_ctx *top_pipe_to_program); - void hwss_add_hubp_wait_pipe_read_start(struct block_sequence_state *seq_state, struct hubp *hubp); -- 2.43.0