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Tue, 11 Aug 2026 10:50:00 -0500 From: James Lin To: CC: Harry Wentland , Leo Li , Aurabindo Pillai , Roman Li , Wayne Lin , Tom Chung , "Fangzhi Zuo" , Dan Wheeler , Ray Wu , Ivan Lipski , Alex Hung , James Lin , Chenyu Chen , Jun Lei , Dillon Varone , James Lin Subject: [PATCH 13/24] drm/amd/display: Add opt-out for DCN6 OutstandingRequests mode-support check Date: Tue, 11 Aug 2026 05:28:47 +0800 Message-ID: <20260810213010.1703162-14-PingLei.Lin@amd.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260810213010.1703162-1-PingLei.Lin@amd.com> References: <20260810213010.1703162-1-PingLei.Lin@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN2PEPF00004FC1:EE_|CH3PR12MB9217:EE_ X-MS-Office365-Filtering-Correlation-Id: bd325802-f5a7-44ed-3cc6-08def7c03c0e X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|1800799024|36860700016|23010399003|82310400026|376014|11063799006|5023799004|56012099006|10067099003|22082099003|18002099003|3023799007; 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DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 3HiTfi9s+Y+pTBR6sb5E8X9RMfI6KUGA8cJTMzxprYwVFldKtgKFB7Q2u+Gf3r0D5+sKjr3V9jJttzoQz0x9YLXPpsSAnifFJm8g1bGlMLj0M4hG1z3g5AxD3Y2LclA8ubahPPECDtI+RcCoaS7CBWnpgJv62W7fgpjh5jLcxxUGYfFcCMVFGfy/DTuLhOH1Mm6X9pAcshg48EoqysbtKjXqvMvpO9UZXz10ZBGRUDqrOWC23vZWiy6+ETr7atcmTR3sJcg5AUZrm4N9u9ixSUXOhZvzIWWsqyeYOP/ZdZE2oBKSmb7cXXQgw9j+uA40mKYsr4fBhlXSDwIbGM3DnlLtWAedkTOoXPP08S7duUcFfkVhzGukHwPcErOeLx8hZeIIbDmh0mo+lpqDQ/tLdo9kt0yH52VFtInI08GGw2iNlwih8y5tvScIy2DWkurA X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Aug 2026 15:50:14.4816 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: bd325802-f5a7-44ed-3cc6-08def7c03c0e X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN2PEPF00004FC1.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB9217 X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" From: Jun Lei The OutstandingRequestsSupport check fails a mode when the outstanding-request buffer window (max_outstanding_reqs * request_size / (DCFCLK * return_bus_width)) is shorter than the average urgent request latency. Because DCFCLK is derived from the SOP's bandwidth, a higher-bandwidth SOP raises DCFCLK, shrinks that window, and perversely makes the mode unsupported - so "too much bandwidth" becomes a failure reason, which defies common sense. When the ROB size / request limit is not yet fixed, the SOP bandwidth/latency values are tuned to a family maximum and the check mis-fires. Add a per-display-config override outstanding_requests_check_disable (overrides.hw, matching the existing *_check_disable idiom) that early-outs the dcn6 check with both flags left supported. Default off, so existing behavior is unchanged. Also wire the flag through the DML JSON translation. Reviewed-by: Dillon Varone Signed-off-by: Jun Lei Signed-off-by: James Lin --- .../dc/dml2_0/dml21/inc/dml_top_display_cfg_types.h | 1 + .../src/dml2_core/dml2_core_dcn6_funcs_mode_support.c | 7 +++++++ 2 files changed, 8 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/dml_top_display_cfg_types.h b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/dml_top_display_cfg_types.h index f402bb933f7d..27ffe7ed11c7 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/dml_top_display_cfg_types.h +++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/dml_top_display_cfg_types.h @@ -487,6 +487,7 @@ struct dml2_display_cfg { bool mode_support_check_disable; bool mcache_admissibility_check_disable; bool surface_viewport_size_check_disable; + bool outstanding_requests_check_disable; double dlg_ref_clk_mhz; double dispclk_mhz; double dcfclk_mhz; diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn6_funcs_mode_support.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn6_funcs_mode_support.c index d83c7eea462b..cb3cff316b0e 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn6_funcs_mode_support.c +++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn6_funcs_mode_support.c @@ -2380,6 +2380,13 @@ static void dcn6_ms_check_average_latency_supports( DML_LOG_FUNC_ENTER(); outputs->support.OutstandingRequestsSupport = true; outputs->support.OutstandingRequestsUrgencyAvoidance = true; + /* An SOP being capable of high bandwidth drives DCFCLK up, which shrinks the outstanding-request + * buffer window below the request latency and (perversely) fails this check. For analysis of future + * SoCs the ROB size / request limit is not yet fixed, so allow the check to be opted out. */ + if (display_cfg->overrides.hw.outstanding_requests_check_disable) { + DML_LOG_FUNC_EXIT(); + return; + } for (k = 0; k < display_cfg->num_planes; k++) { outstanding_latency_us = soc_bb->max_outstanding_reqs * inputs->support.request_size_bytes_luma[k] -- 2.43.0