From: Alex Deucher <alexander.deucher@amd.com>
To: <amd-gfx@lists.freedesktop.org>
Cc: Lijo Lazar <lijo.lazar@amd.com>,
Felix Kuehling <felix.kuehling@amd.com>,
Alex Deucher <alexander.deucher@amd.com>
Subject: [PATCH 78/95] drm/amdgpu: Assign accel state based on ASP config
Date: Fri, 21 Aug 2026 15:34:41 -0400 [thread overview]
Message-ID: <20260821193458.808626-79-alexander.deucher@amd.com> (raw)
In-Reply-To: <20260821193458.808626-1-alexander.deucher@amd.com>
From: Lijo Lazar <lijo.lazar@amd.com>
Add explicit PPOD/VPOD states for clarity. Assign the state accordingly
as received from ASP during initialization.
UALink accel state transitions:
UNCONFIGURED -> PPOD_CONFIGURED -> VPOD_CONFIGURED -> READY -> ACTIVE
- PPOD: sysfs ppod commit/ ASP {UAL_CFG_PPOD}
- VPOD: sysfs vpod commit/ ASP {UAL_CFG_VPOD} | {UAL_CFG_STATION}
- READY: local vpod integrity + activate_accelerator()
- ACTIVE: all local gpus belonging to one vpod are configured and ready.
deactivate_accelerator(): READY -> PPOD_CONFIGURED
invalid vpod: -> ERROR
Query ualink info during late init phase. Add a local vpod integrity
check before activating devices in the vpod. Move the devices to active
state once integrity check passes.
Signed-off-by: Lijo Lazar <lijo.lazar@amd.com>
Reviewed-by: Felix Kuehling <felix.kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 6 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h | 3 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_ualink.c | 320 +++++++++++++++++----
drivers/gpu/drm/amd/amdgpu/amdgpu_ualink.h | 3 +-
4 files changed, 278 insertions(+), 54 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
index b8def8b7e1426..4fc7aed58bfc3 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
@@ -1223,7 +1223,8 @@ int psp_ual_get_interface_version(struct psp_context *psp, uint32_t *intf_ver)
}
int psp_ual_query_info(struct psp_context *psp, uint32_t intf_ver,
- struct amdgpu_ualink_info *info)
+ struct amdgpu_ualink_info *info,
+ enum psp_gfx_ual_config_state *cfg_state)
{
struct psp_gfx_get_config_ual_v1 *ual_config;
struct psp_gfx_cmd_resp *cmd;
@@ -1269,6 +1270,9 @@ int psp_ual_query_info(struct psp_context *psp, uint32_t intf_ver,
if (AMDGPU_UALINK_ACCEL_MAX > PSP_GFX_UAL_MAX_ACC_BIT_MASK*32)
bitmap_clear(info->vpod.active_accel_bits, PSP_GFX_UAL_MAX_ACC_BIT_MASK*32,
AMDGPU_UALINK_ACCEL_MAX - PSP_GFX_UAL_MAX_ACC_BIT_MASK*32);
+
+ if (cfg_state)
+ *cfg_state = ual_config->config_state;
} else if (!ret) {
ret = -EINVAL;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
index bb84f3a3dc54b..2ba7ced36b7cc 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
@@ -715,7 +715,8 @@ struct amdgpu_ualink_station_config;
int psp_ual_get_interface_version(struct psp_context *psp, uint32_t *intf_ver);
int psp_ual_query_info(struct psp_context *psp, uint32_t intf_ver,
- struct amdgpu_ualink_info *info);
+ struct amdgpu_ualink_info *info,
+ enum psp_gfx_ual_config_state *cfg_state);
int psp_ual_set_ppod_config(struct psp_context *psp, uint32_t intf_ver,
const struct amdgpu_ualink_ppod_setup *setup);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ualink.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ualink.c
index d376c3136af8a..a3758c55c0b73 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ualink.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ualink.c
@@ -29,10 +29,12 @@
#include "amdgpu_ualink.h"
#include "amdgpu_xgmi.h"
#include "amdgpu_dma_buf.h"
+#include "psp_gfx_if.h"
#include <linux/sysfs.h>
#include <linux/string.h>
static void deactivate_accelerator(struct amdgpu_device *adev);
+static void amdgpu_ualink_activate_vpod(struct amdgpu_device *adev);
static int amdgpu_ualink_remote_interrupt(struct amdgpu_device *adev,
u32 remote_accel_id, u32 dw0, u32 dw1,
u32 dw2, u32 dw3);
@@ -95,6 +97,113 @@ static void amdgpu_ualink_object_fini(struct amdgpu_device *adev)
adev->ualink.info = NULL;
}
+static bool __check_ppod_info(struct amdgpu_device *adev,
+ const struct amdgpu_ualink_info *info)
+{
+ const struct amdgpu_ualink_ppod_info *ppod = &info->ppod;
+
+ if (ppod->size <= 0 || ppod->size > AMDGPU_UALINK_ACCEL_MAX) {
+ dev_dbg(adev->dev, "pPod size %u out of range [1..%u]\n",
+ ppod->size, AMDGPU_UALINK_ACCEL_MAX);
+ return false;
+ }
+ if (ppod->accel_id >= ppod->size) {
+ dev_dbg(adev->dev,
+ "Accelerator ID %u greater or equal pPod size %u\n",
+ ppod->accel_id, ppod->size);
+ return false;
+ }
+
+ return true;
+}
+
+static bool __check_vpod_info(struct amdgpu_device *adev,
+ const struct amdgpu_ualink_info *info)
+{
+ const struct amdgpu_ualink_ppod_info *ppod = &info->ppod;
+ const struct amdgpu_ualink_vpod_info *vpod = &info->vpod;
+ unsigned int weight;
+
+ if (vpod->size == 0 || vpod->size > ppod->size) {
+ dev_dbg(adev->dev, "vPod size %u out of range [1..%u]\n",
+ vpod->size, ppod->size);
+ return false;
+ }
+ if (vpod->addr_mode >= AMDGPU_UALINK_ADDR_MODE_MAX) {
+ dev_dbg(adev->dev, "Invalid addr mode %u\n", vpod->id);
+ return false;
+ }
+ weight =
+ bitmap_weight(vpod->active_accel_bits, AMDGPU_UALINK_ACCEL_MAX);
+ if (weight != vpod->size) {
+ dev_dbg(adev->dev,
+ "vPod size doesn't match vpod_active_accels list: %u != %u\n",
+ vpod->size, weight);
+ return false;
+ }
+ if (!test_bit(ppod->accel_id, vpod->active_accel_bits)) {
+ dev_dbg(adev->dev,
+ "Accelerator ID %u not listed in vpod_active_accels\n",
+ ppod->accel_id);
+ return false;
+ }
+
+ return true;
+}
+
+static void
+amdgpu_ualink_info_set_accel_state(struct amdgpu_device *adev,
+ struct amdgpu_ualink_info *info,
+ enum psp_gfx_ual_config_state cfg_state)
+{
+ if (!info)
+ return;
+
+ switch (cfg_state) {
+ case UAL_CFG_IDLE:
+ break;
+ case UAL_CFG_PPOD:
+ if (!__check_ppod_info(adev, info)) {
+ info->accel_state =
+ AMDGPU_UALINK_ACCEL_STATE_UNCONFIGURED;
+ break;
+ }
+ info->accel_state = AMDGPU_UALINK_ACCEL_STATE_PPOD_CONFIGURED;
+ break;
+ case UAL_CFG_VPOD:
+ case UAL_CFG_STATION:
+ if (!__check_vpod_info(adev, info)) {
+ info->accel_state = AMDGPU_UALINK_ACCEL_STATE_ERROR;
+ dev_err(adev->dev,
+ "vpod configuration is invalid, setting to error state");
+ break;
+ }
+ info->accel_state = AMDGPU_UALINK_ACCEL_STATE_VPOD_CONFIGURED;
+ break;
+ case UAL_CFG_COMPLETE:
+ info->accel_state = AMDGPU_UALINK_ACCEL_STATE_READY;
+ break;
+ default:
+ dev_dbg(adev->dev, "invalid configuration state %u", cfg_state);
+ break;
+ }
+}
+
+static int amdgpu_ualink_query_info(struct amdgpu_device *adev)
+{
+ enum psp_gfx_ual_config_state cfg_state;
+ int r;
+
+ r = psp_ual_query_info(&adev->psp, adev->ualink.psp_if_ver,
+ adev->ualink.info, &cfg_state);
+ if (r)
+ return r;
+
+ amdgpu_ualink_info_set_accel_state(adev, adev->ualink.info, cfg_state);
+
+ return 0;
+}
+
int ualink_ip_hw_init(struct amdgpu_ip_block *ip_block)
{
struct amdgpu_device *adev = ip_block->adev;
@@ -103,6 +212,7 @@ int ualink_ip_hw_init(struct amdgpu_ip_block *ip_block)
if (!adev->ualink.info)
return 0;
+ adev->ualink.info->accel_state = AMDGPU_UALINK_ACCEL_STATE_UNCONFIGURED;
r = psp_ual_get_interface_version(&adev->psp, &adev->ualink.psp_if_ver);
if (r) {
adev->ualink.psp_if_ver = 0xffffffff;
@@ -114,19 +224,9 @@ int ualink_ip_hw_init(struct amdgpu_ip_block *ip_block)
dev_info(adev->dev, "Found UALink interface version 0x%x\n",
adev->ualink.psp_if_ver);
- r = psp_ual_query_info(&adev->psp, adev->ualink.psp_if_ver,
- adev->ualink.info);
- if (r) {
- dev_info(adev->dev,
- "UALink disabled, failed to query initial config: %d\n",
- r);
- goto disable;
- }
-
adev->ualink.mgr_state = AMDGPU_UALINK_INIT_HW;
return 0;
-
disable:
adev->ualink.mgr_state = AMDGPU_UALINK_INIT_ERROR;
return 0;
@@ -140,6 +240,12 @@ int ualink_ip_late_init(struct amdgpu_ip_block *ip_block)
if (adev->ualink.mgr_state != AMDGPU_UALINK_INIT_HW)
return 0;
+ r = amdgpu_ualink_query_info(adev);
+ if (r)
+ return r;
+
+ amdgpu_ualink_activate_vpod(adev);
+
r = amdgpu_ualink_drm_client_create(adev);
if (r) {
dev_err(adev->dev, "Failed to create UALink DRM client: %d\n",
@@ -406,8 +512,15 @@ static const char * const ualink_addr_mode_values[] = {
"source-aliasing", "source-identification"
};
static const char * const ualink_accel_state_values[] = {
- "unconfigured", "configured", "ready", "active", "error"
+ [AMDGPU_UALINK_ACCEL_STATE_UNCONFIGURED] = "unconfigured",
+ [AMDGPU_UALINK_ACCEL_STATE_PPOD_CONFIGURED] = "ppod_configured",
+ [AMDGPU_UALINK_ACCEL_STATE_VPOD_CONFIGURED] = "vpod_configured",
+ [AMDGPU_UALINK_ACCEL_STATE_READY] = "ready",
+ [AMDGPU_UALINK_ACCEL_STATE_ACTIVE] = "active",
+ [AMDGPU_UALINK_ACCEL_STATE_ERROR] = "error",
};
+static_assert(ARRAY_SIZE(ualink_accel_state_values) ==
+ AMDGPU_UALINK_ACCEL_STATE_MAX);
UALINK_ENUM_SHOW(info, link_type, link_type);
UALINK_VALUE_SHOW(info, accel_id, ppod.accel_id, "%u");
@@ -491,7 +604,7 @@ check_ppod_state(struct amdgpu_device *adev,
setup->ppod.accel_id, setup->ppod.size);
return AMDGPU_UALINK_ACCEL_STATE_UNCONFIGURED;
}
- return AMDGPU_UALINK_ACCEL_STATE_CONFIGURED;
+ return AMDGPU_UALINK_ACCEL_STATE_PPOD_CONFIGURED;
}
static ssize_t ualink_ppod_setup_commit_store(struct kobject *kobj,
@@ -512,7 +625,7 @@ static ssize_t ualink_ppod_setup_commit_store(struct kobject *kobj,
setup);
if (r)
return r;
- r = psp_ual_query_info(&adev->psp, adev->ualink.psp_if_ver, info);
+ r = psp_ual_query_info(&adev->psp, adev->ualink.psp_if_ver, info, NULL);
if (r)
return r;
@@ -581,39 +694,11 @@ UALINK_ENUM_STORE(vpod_config, addr_mode, vpod.addr_mode);
static bool check_vpod_info(struct amdgpu_device *adev,
const struct amdgpu_ualink_info *info)
{
- unsigned int weight;
-
- if (info->accel_state < AMDGPU_UALINK_ACCEL_STATE_CONFIGURED) {
+ if (info->accel_state < AMDGPU_UALINK_ACCEL_STATE_PPOD_CONFIGURED) {
dev_dbg(adev->dev, "pPod is not yet configured\n");
return false;
}
- if (info->vpod.id >= AMDGPU_UALINK_ACCEL_MAX) {
- dev_dbg(adev->dev, "vPod ID %u out of range [0..%u]\n",
- info->vpod.id, AMDGPU_UALINK_ACCEL_MAX - 1);
- return false;
- }
- if (info->vpod.size == 0 || info->vpod.size > info->ppod.size) {
- dev_dbg(adev->dev, "vPod size %u out of range [1..%u]\n",
- info->vpod.size, info->ppod.size);
- return false;
- }
- if (info->vpod.addr_mode >= AMDGPU_UALINK_ADDR_MODE_MAX) {
- dev_dbg(adev->dev, "Invalid addr mode %u\n", info->vpod.id);
- return false;
- }
- weight = bitmap_weight(info->vpod.active_accel_bits, AMDGPU_UALINK_ACCEL_MAX);
- if (weight != info->vpod.size) {
- dev_dbg(adev->dev, "vPod size doesn't match vpod_active_accels list: %u != %u\n",
- info->vpod.size, weight);
- return false;
- }
- if (!test_bit(info->ppod.accel_id, info->vpod.active_accel_bits)) {
- dev_dbg(adev->dev, "Accelerator ID %u not listed in vpod_active_accels\n",
- info->ppod.accel_id);
- return false;
- }
-
- return true;
+ return __check_vpod_info(adev, info);
}
static struct amdgpu_device *find_peer_adev(unsigned int accel_id)
@@ -761,7 +846,7 @@ static void activate_accelerator(struct amdgpu_device *adev)
{
int r;
- if (adev->ualink.info->accel_state >= AMDGPU_UALINK_ACCEL_STATE_READY)
+ if (adev->ualink.info->accel_state >= AMDGPU_UALINK_ACCEL_STATE_ACTIVE)
return;
/* Enable incoming NPA address translation with NPA VMID */
@@ -785,19 +870,20 @@ static void activate_accelerator(struct amdgpu_device *adev)
return;
}
- adev->ualink.info->accel_state = AMDGPU_UALINK_ACCEL_STATE_READY;
+ adev->ualink.info->accel_state = AMDGPU_UALINK_ACCEL_STATE_ACTIVE;
}
static void deactivate_accelerator(struct amdgpu_device *adev)
{
- if (adev->ualink.info->accel_state < AMDGPU_UALINK_ACCEL_STATE_READY)
+ if (adev->ualink.info->accel_state < AMDGPU_UALINK_ACCEL_STATE_ACTIVE)
return;
/* Disable incoming NPA address translation with NPA VMID */
psp_ual_set_npa_config(&adev->psp, adev->ualink.psp_if_ver,
adev->vm_manager.npa_vmid, false);
/* ignore return value */
- adev->ualink.info->accel_state = AMDGPU_UALINK_ACCEL_STATE_CONFIGURED;
+ adev->ualink.info->accel_state =
+ AMDGPU_UALINK_ACCEL_STATE_PPOD_CONFIGURED;
amdgpu_ualink_sw_fini(adev);
amdgpu_ualink_manager_stop(adev);
@@ -822,6 +908,138 @@ static void activate_local_vpod(struct amdgpu_device *adev)
}
}
+static inline bool __is_vpod_peer(struct amdgpu_ualink_info *info,
+ struct amdgpu_ualink_info *peer_info)
+{
+ return peer_info->vpod.id == info->vpod.id &&
+ uuid_equal(&peer_info->ppod.id, &info->ppod.id);
+}
+
+static int __check_local_vpod_integrity(struct amdgpu_device *adev)
+{
+ DECLARE_BITMAP(local_accel_ids, AMDGPU_UALINK_ACCEL_MAX);
+ struct amdgpu_ualink_info *info = adev->ualink.info;
+ u32 local_accels[AMDGPU_UALINK_LOCAL_ACCELS_MAX];
+ struct amdgpu_ualink_info *peer_info;
+ struct amdgpu_device *peer_adev;
+ unsigned int i, n_local_accels;
+ unsigned int accel_id;
+ /* Check that all local accelerators listed in vpod_active_accels have
+ * matching pod IDs
+ */
+ bitmap_zero(local_accel_ids, AMDGPU_UALINK_ACCEL_MAX);
+ n_local_accels = 0;
+ __set_bit(info->ppod.accel_id, local_accel_ids);
+ local_accels[n_local_accels++] = info->ppod.accel_id;
+
+ for (i = 0; i < mgpu_info.num_gpu; i++) {
+ peer_adev = mgpu_info.gpu_ins[i].adev;
+ if (peer_adev == adev || !peer_adev->ualink.info)
+ continue;
+
+ peer_info = peer_adev->ualink.info;
+ /* peer device ppod not configured */
+ if (peer_info->accel_state <
+ AMDGPU_UALINK_ACCEL_STATE_PPOD_CONFIGURED)
+ return -EAGAIN;
+
+ accel_id = peer_info->ppod.accel_id;
+ if (!test_bit(accel_id, info->vpod.active_accel_bits))
+ continue;
+ /* peer device vpod not configured */
+ if (peer_info->accel_state <
+ AMDGPU_UALINK_ACCEL_STATE_VPOD_CONFIGURED)
+ return -EAGAIN;
+
+ if (!uuid_equal(&peer_info->ppod.id, &info->ppod.id)) {
+ dev_dbg(adev->dev,
+ "Peer %u ppod_id doesn't match: %pU != %pU",
+ peer_info->ppod.accel_id, &peer_info->ppod.id,
+ &info->ppod.id);
+ return -EINVAL;
+ }
+
+ if (peer_info->ppod.size != info->ppod.size) {
+ dev_dbg(adev->dev,
+ "Peer %u ppod_size doesn't match: %u != %u\n",
+ accel_id, peer_info->ppod.size,
+ info->ppod.size);
+ return -EINVAL;
+ }
+
+ if (peer_info->vpod.id != info->vpod.id) {
+ dev_dbg(adev->dev,
+ "Peer %u vpod_id doesn't match: %u != %u",
+ accel_id, peer_info->vpod.id, info->vpod.id);
+ return -EINVAL;
+ }
+ if (peer_info->vpod.size != info->vpod.size) {
+ dev_dbg(adev->dev,
+ "Peer %u vpod_size doesn't match: %u != %u\n",
+ accel_id, peer_info->vpod.size,
+ info->vpod.size);
+ return -EINVAL;
+ }
+ if (peer_info->vpod.addr_mode != info->vpod.addr_mode) {
+ dev_dbg(adev->dev,
+ "Peer %u addr_mode doesn't match: %u != %u\n",
+ accel_id, peer_info->vpod.addr_mode,
+ info->vpod.addr_mode);
+ return -EINVAL;
+ }
+ if (!bitmap_equal(peer_info->vpod.active_accel_bits,
+ info->vpod.active_accel_bits,
+ AMDGPU_UALINK_ACCEL_MAX)) {
+ dev_dbg(adev->dev,
+ "Peer %u vpod_active_accels don't match\n",
+ accel_id);
+ return -EINVAL;
+ }
+
+ if (__test_and_set_bit(accel_id, local_accel_ids)) {
+ dev_dbg(adev->dev,
+ "Duplicate accel_id %u among local vpod peers\n",
+ accel_id);
+ return -EINVAL;
+ }
+ local_accels[n_local_accels++] = accel_id;
+ }
+
+ for (i = 0; i < mgpu_info.num_gpu; i++) {
+ peer_adev = mgpu_info.gpu_ins[i].adev;
+ peer_info = peer_adev->ualink.info;
+
+ if (!peer_info)
+ continue;
+ if (peer_adev != adev && !__is_vpod_peer(info, peer_info))
+ continue;
+
+ peer_info->n_local_accels = n_local_accels;
+ memcpy(peer_info->local_accels, local_accels,
+ sizeof(local_accels));
+ }
+
+ return 0;
+}
+
+static void amdgpu_ualink_activate_vpod(struct amdgpu_device *adev)
+{
+ int ret;
+
+ if (adev->ualink.info->accel_state < AMDGPU_UALINK_ACCEL_STATE_READY)
+ return;
+ mutex_lock(&mgpu_info.mutex);
+ ret = __check_local_vpod_integrity(adev);
+ if (ret && ret != -EAGAIN) {
+ dev_err(adev->dev, "Local vpod integrity check failed: %d\n",
+ ret);
+ return;
+ }
+ if (!ret)
+ activate_local_vpod(adev);
+ mutex_unlock(&mgpu_info.mutex);
+}
+
static ssize_t ualink_vpod_config_commit_store(struct kobject *kobj,
struct kobj_attribute *attr,
const char *buf, size_t count)
@@ -835,7 +1053,7 @@ static ssize_t ualink_vpod_config_commit_store(struct kobject *kobj,
if (!sysfs_streq(buf, "true"))
return -EINVAL;
- if (info->accel_state < AMDGPU_UALINK_ACCEL_STATE_CONFIGURED) {
+ if (info->accel_state < AMDGPU_UALINK_ACCEL_STATE_PPOD_CONFIGURED) {
dev_dbg(adev->dev, "Ualink ppod is not yet configured\n");
return -EINVAL;
}
@@ -844,7 +1062,7 @@ static ssize_t ualink_vpod_config_commit_store(struct kobject *kobj,
config);
if (r)
return r;
- r = psp_ual_query_info(&adev->psp, adev->ualink.psp_if_ver, info);
+ r = psp_ual_query_info(&adev->psp, adev->ualink.psp_if_ver, info, NULL);
if (r)
return r;
@@ -858,7 +1076,7 @@ static ssize_t ualink_vpod_config_commit_store(struct kobject *kobj,
mutex_lock(&mgpu_info.mutex);
if (check_local_vpod_integrity(adev))
activate_local_vpod(adev);
- else if (info->accel_state >= AMDGPU_UALINK_ACCEL_STATE_CONFIGURED)
+ else if (info->accel_state >= AMDGPU_UALINK_ACCEL_STATE_PPOD_CONFIGURED)
deactivate_accelerator(adev);
mutex_unlock(&mgpu_info.mutex);
@@ -988,7 +1206,7 @@ static ssize_t ualink_station_config_commit_store(struct kobject *kobj,
r = psp_ual_set_station_config(&adev->psp, adev->ualink.psp_if_ver, stations);
if (r)
return r;
- r = psp_ual_query_info(&adev->psp, adev->ualink.psp_if_ver, info);
+ r = psp_ual_query_info(&adev->psp, adev->ualink.psp_if_ver, info, NULL);
if (r)
return r;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ualink.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ualink.h
index d2348511e61af..18096bdf1272a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ualink.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ualink.h
@@ -103,7 +103,8 @@ enum amdgpu_ualink_type {
enum amdgpu_ualink_accel_state {
AMDGPU_UALINK_ACCEL_STATE_UNCONFIGURED = 0,
- AMDGPU_UALINK_ACCEL_STATE_CONFIGURED,
+ AMDGPU_UALINK_ACCEL_STATE_PPOD_CONFIGURED,
+ AMDGPU_UALINK_ACCEL_STATE_VPOD_CONFIGURED,
AMDGPU_UALINK_ACCEL_STATE_READY,
AMDGPU_UALINK_ACCEL_STATE_ACTIVE,
AMDGPU_UALINK_ACCEL_STATE_ERROR,
--
2.55.0
next prev parent reply other threads:[~2026-08-21 20:00 UTC|newest]
Thread overview: 98+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-08-21 19:33 [PATCH 00/95] Add UALink instrastructure series 1 Alex Deucher
2026-08-21 19:33 ` [PATCH 01/95] drm/amdgpu: Add psp ualink command interfaces Alex Deucher
2026-08-21 19:33 ` [PATCH 02/95] drm/amdgpu: Fetch asp ualink interface version Alex Deucher
2026-08-21 19:33 ` [PATCH 03/95] drm/amdgpu: Add sysfs API for UALink information Alex Deucher
2026-08-21 19:33 ` [PATCH 04/95] drm/amdgpu: Add sysfs API for UALink physical pod setup Alex Deucher
2026-08-21 19:33 ` [PATCH 05/95] drm/amdgpu: Add sysfs API for UALink virtual pod config Alex Deucher
2026-08-21 19:33 ` [PATCH 06/95] drm/amdgpu: Add sysfs API for UALink station configuration Alex Deucher
2026-08-21 19:33 ` [PATCH 07/95] drm/amdgpu: Add UALink manager core infrastructure Alex Deucher
2026-08-21 19:33 ` [PATCH 08/95] drm/amdgpu: Implement PSP cmd UAL_GET_CONFIG Alex Deucher
2026-08-21 19:33 ` [PATCH 09/95] drm/amdgpu: Query initial UALink config from PSP Alex Deucher
2026-08-21 19:33 ` [PATCH 10/95] drm/amdgpu: Implement PSP cmd UAL_SET_PPOD_CONFIG Alex Deucher
2026-08-21 19:33 ` [PATCH 11/95] drm/amdgpu: Set physical pod configuration to PSP Alex Deucher
2026-08-21 19:33 ` [PATCH 12/95] drm/amdgpu: Implement PSP cmd UAL_SET_VPOD_CONFIG Alex Deucher
2026-08-21 19:33 ` [PATCH 13/95] drm/amdgpu: Set virtual pod configuration to PSP Alex Deucher
2026-08-21 19:33 ` [PATCH 14/95] drm/amdgpu: Implement PSP cmd UAL_SET_STATION_CONFIG Alex Deucher
2026-08-21 19:33 ` [PATCH 15/95] drm/amdgpu: Set UALink station config to PSP Alex Deucher
2026-08-21 19:33 ` [PATCH 16/95] drm/amdgpu: Implement PSP cmd UAL_SET_NPA_CONFIG Alex Deucher
2026-08-21 19:33 ` [PATCH 17/95] drm/amdgpu: Enable/disable NPA address translation using PSP Alex Deucher
2026-08-21 19:33 ` [PATCH 18/95] drm/amdgpu: Add helper function to check psp xgmi ta Alex Deucher
2026-08-21 19:33 ` [PATCH 19/95] drm/amdgpu: add handler for nHT error Alex Deucher
2026-08-21 19:33 ` [PATCH 20/95] drm/amdgpu: Add ual_config_state to ual_get_config Alex Deucher
2026-08-21 19:33 ` [PATCH 21/95] drm/amdgpu: extend PSP command polling sleep range Alex Deucher
2026-08-21 19:33 ` [PATCH 22/95] drm/amdgpu: Fix NULL pointer issue during ualink init Alex Deucher
2026-08-21 19:33 ` [PATCH 23/95] drm/amdgpu: Add a new NPA Address space Alex Deucher
2026-08-21 19:33 ` [PATCH 24/95] drm/amdgpu: Add address allocator for NPA addresses Alex Deucher
2026-08-21 19:33 ` [PATCH 25/95] drm/amdgpu: Initialize VM for NPA addr management Alex Deucher
2026-08-21 19:33 ` [PATCH 26/95] drm/amdgpu: Rework VMID reservation logic Alex Deucher
2026-08-21 19:33 ` [PATCH 27/95] drm/amdgpu: Reserve VMID for NPA VM Alex Deucher
2026-08-21 19:33 ` [PATCH 28/95] drm/amdgpu: Use reserved " Alex Deucher
2026-08-21 19:33 ` [PATCH 29/95] drm/amdgpu: Enable UALink Manager when pod becomes active Alex Deucher
2026-08-21 19:33 ` [PATCH 30/95] drm/amdgpu: Fix UALink vPod double-activation Alex Deucher
2026-08-21 19:33 ` [PATCH 31/95] drm/amdgpu: Add UALink remote state structures and API declarations Alex Deucher
2026-08-21 19:33 ` [PATCH 32/95] drm/amdgpu: Add UALink NPA address layout helpers Alex Deucher
2026-08-21 19:33 ` [PATCH 33/95] drm/amdgpu: Add UALink NPA address computation for ring buffers Alex Deucher
2026-08-21 19:33 ` [PATCH 34/95] drm/amdgpu: Add UALink NPA VM mapping " Alex Deucher
2026-08-21 19:33 ` [PATCH 35/95] drm/amdgpu: Add UALink SDMA scheduler entities Alex Deucher
2026-08-21 19:33 ` [PATCH 36/95] drm/amdgpu: Add UALink GART helpers for NPA address access Alex Deucher
2026-08-21 19:34 ` [PATCH 37/95] drm/amdgpu: Add UALink ring buffer allocation and firmware init Alex Deucher
2026-08-21 19:34 ` [PATCH 38/95] drm/amdgpu: Add UALink remote command packets and SDMA dispatch Alex Deucher
2026-08-21 19:34 ` [PATCH 39/95] drm/amdgpu: Add UALink firmware writeback address configuration Alex Deucher
2026-08-21 19:34 ` [PATCH 40/95] drm/amdgpu: Add UALink cross-GPU TLB shootdown and remote interrupt Alex Deucher
2026-08-21 19:34 ` [PATCH 41/95] drm/amdgpu: Add UALink software init, teardown, and reset Alex Deucher
2026-08-21 19:34 ` [PATCH 42/95] drm/amdgpu: Add UALink IH ring and enable interrupt Alex Deucher
2026-08-21 19:34 ` [PATCH 43/95] drm/amdgpu: UALink use LSDMA to send remote interrupt command Alex Deucher
2026-08-21 19:34 ` [PATCH 44/95] drm/amdgpu: Create a drm client for UALink NPA BOs Alex Deucher
2026-08-21 19:34 ` [PATCH 45/95] drm/amdgpu: Control NPA DMA-buf importing Alex Deucher
2026-08-21 19:34 ` [PATCH 46/95] drm/amdgpu: Add ualink handle to BOs Alex Deucher
2026-08-21 19:34 ` [PATCH 47/95] drm/amdgpu: Implement UALink handle export Alex Deucher
2026-08-21 19:34 ` [PATCH 48/95] drm/amdgpu: Add connection state management Alex Deucher
2026-08-21 19:34 ` [PATCH 49/95] drm/amdgpu: Implement UALink handle import ioctl Alex Deucher
2026-08-21 19:34 ` [PATCH 50/95] drm/amdgpu: Implement mechanism to revoke exported memory Alex Deucher
2026-08-21 19:34 ` [PATCH 51/95] drm/amdgpu: lock UALink import invalidation via drm_exec Alex Deucher
2026-08-21 19:34 ` [PATCH 52/95] drm/amdgpu: Cleanup exported UALink handles Alex Deucher
2026-08-21 19:34 ` [PATCH 53/95] drm/amdgpu: Cleanup imported " Alex Deucher
2026-08-21 19:34 ` [PATCH 54/95] drm/amdgpu: Handle connection reset Alex Deucher
2026-08-21 19:34 ` [PATCH 55/95] drm/amdgpu: Setup PTE mappings for NPA addresses Alex Deucher
2026-08-21 19:34 ` [PATCH 56/95] drm/amdgpu: Add handling for remote interrupts Alex Deucher
2026-08-21 19:34 ` [PATCH 57/95] drm/amdgpu: Send TLB shootdown on exported memory unmap Alex Deucher
2026-08-21 19:34 ` [PATCH 58/95] drm/amdgpu: Handle local GPUs in UALink import Alex Deucher
2026-08-21 19:34 ` [PATCH 59/95] drm/amdgpu: Add debugfs to drop UALink protocol messages Alex Deucher
2026-08-21 19:34 ` [PATCH 60/95] drm/amdgpu: Temporarily disable sending remote TLB shootdowns Alex Deucher
2026-08-21 19:34 ` [PATCH 61/95] drm/amdgpu: Temporarily Flush TLB on NPA mapping always Alex Deucher
2026-08-21 19:34 ` [PATCH 62/95] drm/amdgpu: log remote memory MTYPE for GC 12.1.0 Alex Deucher
2026-08-21 19:34 ` [PATCH 63/95] drm/amdgpu: Prevent double-free of drm_exec Alex Deucher
2026-08-21 19:34 ` [PATCH 64/95] drm/amdgpu: fix NPA-RELEASE race in UALink exporter cleanup Alex Deucher
2026-08-21 19:34 ` [PATCH 65/95] drm/amdgpu: initialize UALink importer node list head Alex Deucher
2026-08-21 19:34 ` [PATCH 66/95] drm/amdgpu: Fix initialization flags for UALink XAs Alex Deucher
2026-08-21 19:34 ` [PATCH 67/95] drm/amdgpu: fix dma_buf leak in UALink exporter cleanup Alex Deucher
2026-08-21 19:34 ` [PATCH 68/95] drm/amdgpu: Increase UALink soft ring size Alex Deucher
2026-08-21 19:34 ` [PATCH 69/95] drm/amdgpu: Fix uninitialized fence in UALink NPA unmap Alex Deucher
2026-08-21 19:34 ` [PATCH 70/95] drm/amdgpu: Use vm->last_update fence in UALink NPA unmap paths Alex Deucher
2026-08-21 19:34 ` [PATCH 71/95] drm/amdgpu: Pin page tables in NPA VMs Alex Deucher
2026-08-21 19:34 ` [PATCH 72/95] drm/amdgpu: Initialize NPA PT/PDs to noretry Alex Deucher
2026-08-21 19:34 ` [PATCH 73/95] drm/amdgpu: always use MTYPE_UC for remote memory on GFX 12.1 Alex Deucher
2026-08-21 19:34 ` [PATCH 74/95] drm/amdkfd: program compute MQD coherent_aql_mtype " Alex Deucher
2026-08-21 19:34 ` [PATCH 75/95] drm/amdgpu: Separate out ualink init sequences Alex Deucher
2026-08-21 19:34 ` [PATCH 76/95] drm/amdgpu: Add ualink as separate ip block Alex Deucher
2026-08-21 19:34 ` [PATCH 77/95] drm/admgpu: Seggregate ualink nht messaging Alex Deucher
2026-08-21 19:34 ` Alex Deucher [this message]
2026-08-21 19:34 ` [PATCH 79/95] drm/amdgpu: Drop duplicate vpod check functions Alex Deucher
2026-08-21 19:34 ` [PATCH 80/95] drm/amdgpu: Add support to send ASP completion Alex Deucher
2026-08-21 19:34 ` [PATCH 81/95] drm/amdgpu: Add handlers for ualink notifications Alex Deucher
2026-08-21 19:34 ` [PATCH 82/95] drm/amdgpu: Improve ualink state transitions Alex Deucher
2026-08-21 19:34 ` [PATCH 83/95] drm/amdgpu: Use uniform logic for inband/sideband Alex Deucher
2026-08-21 19:34 ` [PATCH 84/95] drm/amdgpu: Fix GART and SDMA entity leak on vPod reconfiguration Alex Deucher
2026-08-21 19:34 ` [PATCH 85/95] drm/amdgpu: Add UALink diagnostic logging for vpod commit/activation Alex Deucher
2026-08-21 19:34 ` [PATCH 86/95] drm/amdgpu: Handle UALink vPod reconfiguration while ACTIVE Alex Deucher
2026-08-21 19:34 ` [PATCH 87/95] drm/amdgpu: Add name for ualink ip block Alex Deucher
2026-08-21 19:34 ` [PATCH 88/95] drm/amdgpu: Cleanup UALink XA entries on manager stop Alex Deucher
2026-08-21 19:34 ` [PATCH 89/95] drm/amdgpu: Move ualink ip version related changes Alex Deucher
2026-08-21 19:34 ` [PATCH 90/95] drm/amdgpu: Add hw_fini for ualink Alex Deucher
2026-08-21 19:34 ` [PATCH 91/95] drm/amdgpu: Expose ualink info under each xcp Alex Deucher
2026-08-21 19:34 ` [PATCH 92/95] drm/amdgpu: Handle concurrent UALINK handle import race Alex Deucher
2026-08-21 19:34 ` [PATCH 93/95] drm/amdgpu: create UALink NPA import BO directly in the NPA domain Alex Deucher
2026-08-21 19:34 ` [PATCH 94/95] drm/amdgpu: add mtype_remote module parameter Alex Deucher
2026-08-21 19:34 ` [PATCH 95/95] drm/amdgpu: Honor mtype overrides for NPA remote memory Alex Deucher
2026-08-25 14:45 ` [PATCH 00/95] Add UALink instrastructure series 1 Philip Yang
-- strict thread matches above, loose matches on Subject: below --
2026-08-31 18:26 [PATCH V2 00/95] Add UALink infrastructure " Alex Deucher
2026-08-31 18:27 ` [PATCH 78/95] drm/amdgpu: Assign accel state based on ASP config Alex Deucher
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