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[94.27.154.94]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c255f29a9dfsm75364066b.63.2026.08.28.05.07.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Aug 2026 05:07:34 -0700 (PDT) From: =?UTF-8?q?Timur=20Krist=C3=B3f?= To: amd-gfx@lists.freedesktop.org, Alexander.Deucher@amd.com, =?UTF-8?q?Christian=20K=C3=B6nig?= , Natalie Vock , =?UTF-8?q?Marek=20Ol=C5=A1=C3=A1k?= , Mario Limonciello , Tvrtko Ursulin , Felix Kuehling , Lijo Lazar Cc: =?UTF-8?q?Timur=20Krist=C3=B3f?= Subject: [PATCH 1/5] drm/amdgpu/sdma: Clear SDMA rings after reset before starting them Date: Fri, 28 Aug 2026 14:07:25 +0200 Message-ID: <20260828120729.25908-2-timur.kristof@gmail.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260828120729.25908-1-timur.kristof@gmail.com> References: <20260828120729.25908-1-timur.kristof@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" The ring contains commands that were emitted before the reset. These need to be cleared to make sure the HW doesn't execute them, because they are garbage at this point. Note that the ring reset helpers will re-emit the commands that are necessary after the reset. Signed-off-by: Timur Kristóf --- drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c index fbac732f3e01..66f278f77f71 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c @@ -593,6 +593,18 @@ int amdgpu_sdma_reset_engine(struct amdgpu_device *adev, uint32_t instance_id, goto exit; } + amdgpu_ring_clear_ring(gfx_ring); + gfx_ring->wptr = 0; + atomic64_set((atomic64_t *)gfx_ring->wptr_cpu_addr, 0); + atomic64_set((atomic64_t *)gfx_ring->rptr_cpu_addr, 0); + + if (adev->sdma.has_page_queue) { + amdgpu_ring_clear_ring(page_ring); + page_ring->wptr = 0; + atomic64_set((atomic64_t *)page_ring->wptr_cpu_addr, 0); + atomic64_set((atomic64_t *)page_ring->rptr_cpu_addr, 0); + } + if (sdma_instance->funcs->start_kernel_queue) { sdma_instance->funcs->start_kernel_queue(gfx_ring); if (adev->sdma.has_page_queue) -- 2.55.0