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Ip=[165.204.84.17]; Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN2PEPF0000A802.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ2PR12MB9240 X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" SMU 15.0.8 applies default GFXCLK and UCLK ranges directly from reset. Stage the defaults instead, leaving c as the only PMFW update operation. Only stage and commit UCLK when its DPM feature is enabled. This matches the edit path and avoids sending an unsupported UCLK limit command. Signed-off-by: Kevin Wang --- .../drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.c | 50 ++++++++++--------- 1 file changed, 27 insertions(+), 23 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.c index db0e0733588d..0f7a8b4585d2 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.c @@ -2072,6 +2072,28 @@ static int smu_v15_0_8_set_soft_freq_limited_range(struct smu_context *smu, return ret; } +static void smu_v15_0_8_stage_default_dpm_limits(struct smu_context *smu) +{ + struct smu_dpm_context *smu_dpm = &smu->smu_dpm; + struct smu_15_0_dpm_context *dpm_context = smu_dpm->dpm_context; + struct smu_umd_pstate_table *pstate_table = &smu->pstate_table; + + pstate_table->gfxclk_pstate.custom.min = + SMU_DPM_TABLE_MIN(&dpm_context->dpm_tables.gfx_table); + pstate_table->gfxclk_pstate.custom.max = + SMU_DPM_TABLE_MAX(&dpm_context->dpm_tables.gfx_table); + + if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) { + pstate_table->uclk_pstate.custom.min = + SMU_DPM_TABLE_MIN(&dpm_context->dpm_tables.uclk_table); + pstate_table->uclk_pstate.custom.max = + SMU_DPM_TABLE_MAX(&dpm_context->dpm_tables.uclk_table); + } else { + pstate_table->uclk_pstate.custom.min = 0; + pstate_table->uclk_pstate.custom.max = 0; + } +} + static int smu_v15_0_8_od_edit_dpm_table(struct smu_context *smu, enum PP_OD_DPM_TABLE_COMMAND type, long input[], uint32_t size) @@ -2159,27 +2181,7 @@ static int smu_v15_0_8_od_edit_dpm_table(struct smu_context *smu, return -EINVAL; } - /* Use the default frequencies for manual mode */ - min_clk = SMU_DPM_TABLE_MIN(&dpm_context->dpm_tables.gfx_table); - max_clk = SMU_DPM_TABLE_MAX(&dpm_context->dpm_tables.gfx_table); - - ret = smu_v15_0_8_set_soft_freq_limited_range(smu, - SMU_GFXCLK, - min_clk, max_clk, - false); - if (ret) - return ret; - - min_clk = SMU_DPM_TABLE_MIN(&dpm_context->dpm_tables.uclk_table); - max_clk = SMU_DPM_TABLE_MAX(&dpm_context->dpm_tables.uclk_table); - ret = smu_v15_0_8_set_soft_freq_limited_range(smu, - SMU_UCLK, - min_clk, max_clk, - false); - if (ret) - return ret; - - smu_cmn_reset_custom_level(smu); + smu_v15_0_8_stage_default_dpm_limits(smu); break; case PP_OD_COMMIT_DPM_TABLE: if (size != 0) { @@ -2207,8 +2209,10 @@ static int smu_v15_0_8_od_edit_dpm_table(struct smu_context *smu, return ret; /* Commit UCLK custom range (only max supported) */ - if (pstate_table->uclk_pstate.custom.max) { - min_clk = pstate_table->uclk_pstate.curr.min; + if (pstate_table->uclk_pstate.custom.max && + smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) { + min_clk = pstate_table->uclk_pstate.custom.min ?: + pstate_table->uclk_pstate.curr.min; max_clk = pstate_table->uclk_pstate.custom.max; ret = smu_v15_0_8_set_soft_freq_limited_range(smu, SMU_UCLK, -- 2.55.0