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Mon, 31 Aug 2026 09:26:32 -0500 Received: from Xiaogang-ROCM-Dev.amd.com (10.180.168.240) by satlexmb08.amd.com (10.181.42.217) with Microsoft SMTP Server id 15.2.2562.46 via Frontend Transport; Mon, 31 Aug 2026 09:26:31 -0500 From: Xiaogang.Chen To: CC: Xiaogang Chen Subject: [PATCH 4/4] drm/amdkfd: Apply AMDGPU_PTE_FRAG to pte of gart page table for THP mapping Date: Mon, 31 Aug 2026 09:24:18 -0500 Message-ID: <20260831142418.56423-5-xiaogang.chen@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260831142418.56423-1-xiaogang.chen@amd.com> References: <20260831142418.56423-1-xiaogang.chen@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MWH0EPF000A6735:EE_|DS0PR12MB6631:EE_ X-MS-Office365-Filtering-Correlation-Id: acdc1a2c-56a3-4a51-e7cd-08df076bdbc7 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|82310400026|23010399003|36860700016|1800799024|376014|3023799007|11063799006|56012099006|10067099003|18002099003|22082099003; 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DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 1MsNVDMVbJ7lWQI5xqZKAunfSVcWMCx0/+CWwjVEzBEwQAEnQwDeNxFjeeH5gm1dWxbi2V9WwFL4m78ND+DGD4mDFwyGeNVIQ1jHiZpjXsG+NZLiQ1iQ9l/184eJIR6Z75cJbmGbR/QQFlfyaZUxzQYvpiGvnkcodeh1ehqWRWp2JecZ68qFhgSBtNgQiO2WnBbuNybYYzYawHUUiVbZUPisg6Fu/M+sgPVkux3v2CnHVhPRuszXxNw898u/66aSxsSRxmSvoNqpYToFBx68jITbsB/Xnqt34Ja/YRR/aVVW66hFcFf9BOKm5veUPQF/uH84jWcE8MfFMqZKXYt4DoMfIA7/VnpJS1ukjWwbSt7FmOy5+XprtAE0pxHjGlwWlS8AXBBshQ0W/H2dspklPWltl0DgEr+6AZ1VlBx0Rm0E13qvOrlhZ7+XN9//6pfi X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 31 Aug 2026 14:26:33.8748 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: acdc1a2c-56a3-4a51-e7cd-08df076bdbc7 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[satlexmb08.amd.com] X-MS-Exchange-CrossTenant-AuthSource: MWH0EPF000A6735.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB6631 X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" From: Xiaogang Chen When both sys ram and vram are physical continuous HPAGE_PMD_NR pages during migration set AMDGPU_PTE_FRAG(HPAGE_PMD_ORDER) at pte in gart page table to let hardware know the migrating pages are HPAGE_PMD_NR size THP. That will reduce hardware TLB pressure or increase TLB hit ration. Signed-off-by: Xiaogang Chen --- drivers/gpu/drm/amd/amdkfd/kfd_migrate.c | 43 ++++++++++++++---------- 1 file changed, 26 insertions(+), 17 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c b/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c index 30eac5fbcde5..6863be041ba5 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c @@ -48,7 +48,7 @@ static int svm_migrate_gart_map(struct amdgpu_ring *ring, struct amdgpu_ttm_buffer_entity *entity, u64 npages, - dma_addr_t *addr, u64 *gart_addr, u64 flags) + dma_addr_t *addr, u64 *gart_addr, u64 flags, bool is_thp) { struct amdgpu_device *adev = ring->adev; struct amdgpu_job *job; @@ -90,6 +90,9 @@ svm_migrate_gart_map(struct amdgpu_ring *ring, pte_flags |= AMDGPU_PTE_WRITEABLE; pte_flags |= adev->gart.gart_pte_flags; + if (is_thp) + pte_flags |= AMDGPU_PTE_FRAG(HPAGE_PMD_ORDER); + cpu_addr = &job->ibs[0].ptr[num_dw]; amdgpu_gart_map(adev, 0, npages, addr, pte_flags, cpu_addr); @@ -108,6 +111,7 @@ svm_migrate_gart_map(struct amdgpu_ring *ring, * @npages: number of pages to copy * @direction: enum MIGRATION_COPY_DIR * @mfence: output, sdma fence to signal after sdma is done + * @is_thp: both sys and vram are physical continuous HPAGE_PMD_NR pages * * ram address uses GART table continuous entries mapping to ram pages, * vram address uses direct mapping of vram pages, which must have npages @@ -126,7 +130,7 @@ static int svm_migrate_copy_memory_gart(struct amdgpu_device *adev, dma_addr_t *sys, u64 *vram, u64 npages, enum MIGRATION_COPY_DIR direction, - struct dma_fence **mfence) + struct dma_fence **mfence, bool is_thp) { const u64 GTT_MAX_PAGES = (AMDGPU_GTT_MAX_TRANSFER_SIZE >> PAGE_SHIFT); struct amdgpu_ring *ring; @@ -136,6 +140,12 @@ svm_migrate_copy_memory_gart(struct amdgpu_device *adev, dma_addr_t *sys, u64 size; int r = 0; + if (is_thp && npages != HPAGE_PMD_NR) { + dev_warn(adev->dev, "THP migration should have %d pages\n", + HPAGE_PMD_NR); + is_thp = false; + } + ring = to_amdgpu_ring(adev->mman.buffer_funcs_scheds[0]); entity = &adev->mman.move_entities[0]; @@ -146,11 +156,12 @@ svm_migrate_copy_memory_gart(struct amdgpu_device *adev, dma_addr_t *sys, if (direction == FROM_VRAM_TO_RAM) { gart_s = svm_migrate_direct_mapping_addr(adev, *vram); - r = svm_migrate_gart_map(ring, entity, size, sys, &gart_d, 0); + r = svm_migrate_gart_map(ring, entity, size, sys, &gart_d, 0, + is_thp); } else if (direction == FROM_RAM_TO_VRAM) { r = svm_migrate_gart_map(ring, entity, size, sys, &gart_s, - KFD_IOCTL_SVM_FLAG_GPU_RO); + KFD_IOCTL_SVM_FLAG_GPU_RO, is_thp); gart_d = svm_migrate_direct_mapping_addr(adev, *vram); } if (r) { @@ -353,7 +364,7 @@ svm_migrate_copy_to_vram(struct kfd_node *node, struct svm_range *prange, adev, src + i - j, dst + i - j, j, FROM_RAM_TO_VRAM, - mfence); + mfence, false); if (r) goto out_free_vram_pages; @@ -389,7 +400,7 @@ svm_migrate_copy_to_vram(struct kfd_node *node, struct svm_range *prange, adev, src + i, dst + i, HPAGE_PMD_NR, FROM_RAM_TO_VRAM, - mfence); + mfence, true); if (r) goto out_free_vram_pages; @@ -417,7 +428,7 @@ svm_migrate_copy_to_vram(struct kfd_node *node, struct svm_range *prange, adev, src + i - j, dst + i - j, j, FROM_RAM_TO_VRAM, - mfence); + mfence, false); if (r) goto out_free_vram_pages; @@ -436,7 +447,7 @@ svm_migrate_copy_to_vram(struct kfd_node *node, struct svm_range *prange, r = svm_migrate_copy_memory_gart(adev, src + i - j, dst + i - j, j, FROM_RAM_TO_VRAM, - mfence); + mfence, false); if (r) goto out_free_vram_pages; } @@ -450,7 +461,7 @@ svm_migrate_copy_to_vram(struct kfd_node *node, struct svm_range *prange, if (j > 0) r = svm_migrate_copy_memory_gart(adev, src + i - j, dst + i - j, j, - FROM_RAM_TO_VRAM, mfence); + FROM_RAM_TO_VRAM, mfence, false); out_free_vram_pages: if (r) { @@ -719,7 +730,7 @@ svm_migrate_copy_to_ram(struct amdgpu_device *adev, struct svm_range *prange, r = svm_migrate_copy_memory_gart(adev, dst + i - j, src + i - j, j, FROM_VRAM_TO_RAM, - mfence); + mfence, false); if (r) goto out_oom; j = 0; @@ -734,7 +745,7 @@ svm_migrate_copy_to_ram(struct amdgpu_device *adev, struct svm_range *prange, r = svm_migrate_copy_memory_gart(adev, dst + i - j, src + i - j, j, FROM_VRAM_TO_RAM, - mfence); + mfence, false); if (r) goto out_oom; j = 0; @@ -777,7 +788,8 @@ svm_migrate_copy_to_ram(struct amdgpu_device *adev, struct svm_range *prange, /* migrate previous accumulated pages */ if(j) { r = svm_migrate_copy_memory_gart(adev, dst + i - j, - src + i - j, j, FROM_VRAM_TO_RAM, mfence); + src + i - j, j, FROM_VRAM_TO_RAM, + mfence, false); if (r) goto out_oom; j = 0; @@ -791,14 +803,11 @@ svm_migrate_copy_to_ram(struct amdgpu_device *adev, struct svm_range *prange, } /* migrate the HPAGE_PMD_NR pages above */ - /* svm_migrate_copy_memory_gart will add a paramter to indicate - * the migration is for 2MB THP - */ r = svm_migrate_copy_memory_gart( adev, dst + i, src + i, HPAGE_PMD_NR, FROM_VRAM_TO_RAM, - mfence); + mfence, true); if (r) goto out_oom; @@ -812,7 +821,7 @@ svm_migrate_copy_to_ram(struct amdgpu_device *adev, struct svm_range *prange, if (j > 0) r = svm_migrate_copy_memory_gart(adev, dst + i - j, src + i - j, j, - FROM_VRAM_TO_RAM, mfence); + FROM_VRAM_TO_RAM, mfence, false); out_oom: if (r) { pr_debug("failed %d copy to ram\n", r); -- 2.34.1