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[79.129.242.108]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-49cdce08b8esm47139235e9.3.2026.09.01.01.41.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 01 Sep 2026 01:41:33 -0700 (PDT) From: =?UTF-8?q?Timur=20Krist=C3=B3f?= To: amd-gfx@lists.freedesktop.org, Alexander.Deucher@amd.com, =?UTF-8?q?Christian=20K=C3=B6nig?= , Natalie Vock , Tvrtko Ursulin , Felix Kuehling , Lijo Lazar Cc: =?UTF-8?q?Timur=20Krist=C3=B3f?= Subject: [PATCH 6/8] drm/amdgpu/sdma: Move SDMA v5.x queue reset to common code Date: Tue, 1 Sep 2026 10:41:13 +0200 Message-ID: <20260901084115.262457-7-timur.kristof@gmail.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260901084115.262457-1-timur.kristof@gmail.com> References: <20260901084115.262457-1-timur.kristof@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" The code was exactly the same between SDMA v5.0 and v5.2 furthermore the exact same implementation can be shared between all SDMA versions that don't use MES. Signed-off-by: Timur Kristóf --- drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c | 37 ++++++++++++++++++++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h | 4 +++ drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c | 25 +--------------- drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c | 25 +--------------- 4 files changed, 43 insertions(+), 48 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c index 66f278f77f71..9eebd8380834 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c @@ -635,3 +635,40 @@ int amdgpu_sdma_reset_engine(struct amdgpu_device *adev, uint32_t instance_id, return ret; } + +/** + * amdgpu_sdma_reset_queue_legacy() - Reset legacy SDMA queue after timeout (without MES) + * + * @ring: Pointer to the ring of the SDMA queue + * @vmid: VMID of the timed out job + * @timedout_fence: Fence of the timed out job + * + * Common implementation for resetting SDMA queues without MES (legacy). + * This relies on the proper amdgpu_sdma_funcs to be set up + * for the given ring. + * + * Applicable to SDMA versions that don't rely on the MES yet, + * that is all versions up to SDMA v5.x and older. + */ +int amdgpu_sdma_reset_queue_legacy(struct amdgpu_ring *ring, + unsigned int vmid, + struct amdgpu_fence *timedout_fence) +{ + struct amdgpu_device *adev = ring->adev; + int r; + + if (ring->me >= adev->sdma.num_instances) { + dev_err(adev->dev, "sdma instance not found\n"); + return -EINVAL; + } + + amdgpu_ring_reset_helper_begin(ring, timedout_fence); + + amdgpu_amdkfd_suspend(adev, true); + r = amdgpu_sdma_reset_engine(adev, ring->me, true); + amdgpu_amdkfd_resume(adev, true); + if (r) + return r; + + return amdgpu_ring_reset_helper_end(ring, timedout_fence); +} diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h index 055dd2522ecd..cb41453c1a19 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h @@ -156,6 +156,10 @@ struct amdgpu_buffer_funcs { int amdgpu_sdma_reset_engine(struct amdgpu_device *adev, uint32_t instance_id, bool caller_handles_kernel_queues); +int amdgpu_sdma_reset_queue_legacy(struct amdgpu_ring *ring, + unsigned int vmid, + struct amdgpu_fence *timedout_fence); + #define amdgpu_emit_copy_buffer(adev, ib, s, d, b, t) (adev)->mman.buffer_funcs->emit_copy_buffer((ib), (s), (d), (b), (t)) #define amdgpu_emit_fill_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_fill_buffer((ib), (s), (d), (b)) diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c index b7bda6361ef9..86eef0a361a7 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c @@ -1491,29 +1491,6 @@ static int sdma_v5_0_wait_for_idle(struct amdgpu_ip_block *ip_block) return -ETIMEDOUT; } -static int sdma_v5_0_reset_queue(struct amdgpu_ring *ring, - unsigned int vmid, - struct amdgpu_fence *timedout_fence) -{ - struct amdgpu_device *adev = ring->adev; - int r; - - if (ring->me >= adev->sdma.num_instances) { - dev_err(adev->dev, "sdma instance not found\n"); - return -EINVAL; - } - - amdgpu_ring_reset_helper_begin(ring, timedout_fence); - - amdgpu_amdkfd_suspend(adev, true); - r = amdgpu_sdma_reset_engine(adev, ring->me, true); - amdgpu_amdkfd_resume(adev, true); - if (r) - return r; - - return amdgpu_ring_reset_helper_end(ring, timedout_fence); -} - static int sdma_v5_0_stop_queue(struct amdgpu_ring *ring) { u32 f32_cntl, freeze, cntl, stat1_reg; @@ -1909,7 +1886,7 @@ static const struct amdgpu_ring_funcs sdma_v5_0_ring_funcs = { .emit_reg_write_reg_wait = sdma_v5_0_ring_emit_reg_write_reg_wait, .init_cond_exec = sdma_v5_0_ring_init_cond_exec, .preempt_ib = sdma_v5_0_ring_preempt_ib, - .reset = sdma_v5_0_reset_queue, + .reset = amdgpu_sdma_reset_queue_legacy, }; static void sdma_v5_0_set_ring_funcs(struct amdgpu_device *adev) diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c index d063babab833..09f00c99dd70 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c @@ -1409,29 +1409,6 @@ static int sdma_v5_2_wait_for_idle(struct amdgpu_ip_block *ip_block) return -ETIMEDOUT; } -static int sdma_v5_2_reset_queue(struct amdgpu_ring *ring, - unsigned int vmid, - struct amdgpu_fence *timedout_fence) -{ - struct amdgpu_device *adev = ring->adev; - int r; - - if (ring->me >= adev->sdma.num_instances) { - dev_err(adev->dev, "sdma instance not found\n"); - return -EINVAL; - } - - amdgpu_ring_reset_helper_begin(ring, timedout_fence); - - amdgpu_amdkfd_suspend(adev, true); - r = amdgpu_sdma_reset_engine(adev, ring->me, true); - amdgpu_amdkfd_resume(adev, true); - if (r) - return r; - - return amdgpu_ring_reset_helper_end(ring, timedout_fence); -} - static int sdma_v5_2_stop_queue(struct amdgpu_ring *ring) { u32 f32_cntl, freeze, cntl, stat1_reg; @@ -1924,7 +1901,7 @@ static const struct amdgpu_ring_funcs sdma_v5_2_ring_funcs = { .emit_reg_write_reg_wait = sdma_v5_2_ring_emit_reg_write_reg_wait, .init_cond_exec = sdma_v5_2_ring_init_cond_exec, .preempt_ib = sdma_v5_2_ring_preempt_ib, - .reset = sdma_v5_2_reset_queue, + .reset = amdgpu_sdma_reset_queue_legacy, }; static void sdma_v5_2_set_ring_funcs(struct amdgpu_device *adev) -- 2.55.0