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Thu, 3 Sep 2026 04:44:45 -0500 Received: from JesseDEV.amd.com (10.180.168.240) by satlexmb07.amd.com (10.181.42.216) with Microsoft SMTP Server id 15.2.2562.46 via Frontend Transport; Thu, 3 Sep 2026 04:44:44 -0500 From: Jesse Zhang To: CC: , Christian Koenig , Jesse Zhang Subject: [PATCH 4/4] drm/amdgpu/userq: reset a hung SDMA user queue over MMIO Date: Thu, 3 Sep 2026 17:42:06 +0800 Message-ID: <20260903094438.3880682-4-Jesse.Zhang@amd.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20260903094438.3880682-1-Jesse.Zhang@amd.com> References: <20260903094438.3880682-1-Jesse.Zhang@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN1PEPF00005FFD:EE_|SN7PR12MB7203:EE_ X-MS-Office365-Filtering-Correlation-Id: 0178a8f7-9473-4059-9481-08df099ffd2f X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|36860700016|376014|1800799024|23010399003|82310400026|10067099003|11063799006|56012099006|18002099003|22082099003; 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DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: whcGz1YGxk44HKXGVeN5WA6cmF2ay/POwSn/4qRZoDl1Tl4iCXr/ZQkR5G5+LxHOq9kxkIeMsbN23EDU3SnkGJqFMuI3jqtQe25goDKmCuJLPNJPzkQaR3ix0cXRSnIZ3b9vXzsEY+LLijIijQS9XQOtZ5ebpxYzo/4ODkTyRtGSToDAss/XY4aFTe9NwWp965mx8HJjsxCq0/M6y04sKw9qRfqtIuzCJkpRasrWZFJ7XAJCz+kHkLf0ULccEzhQpM1qRWUtWYPvLL+nb+0xy1SFL4J0MqckCLRvQMgL4CBeI9ROYOeeaYXk+p8b8+S8Dx6MAfDpuOiPflg8pS/jY0ndb1hoBuAiEMgqmVPU9nNgGYlTdIejd0x4LQV+tVvedv0MSR6WIRIKyA4VMhPD10jaq0fQj2k2z0G3p0Rxxo9qkHsPsmEX9l3NZn0edcto X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 Sep 2026 09:44:46.1680 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 0178a8f7-9473-4059-9481-08df099ffd2f X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN1PEPF00005FFD.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR12MB7203 X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" A hung SDMA user queue wedges MES, so the MES packet reset times out and falls back to a full MODE1 reset - once per in-flight job, a reset storm. The queue is still on its HW slot at the first hang-detect, so use detect_hung_queue to recover its slot from the doorbell and reset it over MMIO, which does not need MES. Mark it HUNG (not UNMAPPED) so the restore worker does not re-map and re-run the guilty job, and short-circuit the per-fence hang-detect re-entry once the queue is already reset. Signed-off-by: Jesse Zhang --- drivers/gpu/drm/amd/amdgpu/mes_userqueue.c | 48 ++++++++++++++++++---- 1 file changed, 39 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/mes_userqueue.c b/drivers/gpu/drm/amd/amdgpu/mes_userqueue.c index 46ebc002548d..2ce94cd04fd5 100644 --- a/drivers/gpu/drm/amd/amdgpu/mes_userqueue.c +++ b/drivers/gpu/drm/amd/amdgpu/mes_userqueue.c @@ -213,26 +213,56 @@ int mes_userq_reset(struct amdgpu_usermode_queue *queue) struct mes_reset_queue_input queue_input; int r; - /* XXX: add a FW version check for SDMA per queue reset */ + /* already reset by an earlier job's hang-detect; just signal and bail */ + if (queue->state == AMDGPU_USERQ_STATE_HUNG) { + amdgpu_userq_fence_driver_force_completion(queue); + return 0; + } + memset(&queue_input, 0x0, sizeof(struct mes_reset_queue_input)); queue_input.doorbell_offset = queue->doorbell_index; queue_input.queue_type = queue->queue_type; + /* + * The MES packet reset fails once the hung queue wedges MES. For SDMA the + * queue is still on its HW slot, so reset it over MMIO instead: recover + * the (instance, queue_id) slot from the doorbell. + */ + if (queue->queue_type == AMDGPU_HW_IP_DMA && + adev->sdma.instance[0].funcs && + adev->sdma.instance[0].funcs->detect_hung_queue) { + u32 instance, hw_queue_id; + + if (adev->sdma.instance[0].funcs->detect_hung_queue(adev, + queue->doorbell_index, &instance, &hw_queue_id)) { + queue_input.use_mmio = true; + queue_input.me_id = instance; + queue_input.queue_id = hw_queue_id; + } else { + dev_warn(adev->dev, + "SDMA userq (doorbell %llu) not on any HW slot; falling back to MES reset\n", + queue->doorbell_index); + } + } + + /* HUNG, not UNMAPPED: the guilty job is still in the ring, so the + * restore worker must not re-map and re-run it. + */ + queue->state = AMDGPU_USERQ_STATE_HUNG; + amdgpu_mes_lock(&adev->mes); r = adev->mes.funcs->reset_hw_queue(&adev->mes, &queue_input); amdgpu_mes_unlock(&adev->mes); if (r) return r; - /* mes_userq_unmap() does not update queue->state; mark it UNMAPPED so the - * destroy path does not issue a second REMOVE_QUEUE for the removed queue. - */ + /* drop the queue from MES and force-complete its fences */ r = mes_userq_unmap(queue); - if (!r) { - trace_amdgpu_userq_state_changed(queue, AMDGPU_USERQ_STATE_UNMAPPED); - queue->state = AMDGPU_USERQ_STATE_UNMAPPED; - } - return r; + if (r) + return r; + + amdgpu_userq_fence_driver_force_completion(queue); + return 0; } int mes_userq_reset_queue(struct amdgpu_device *adev, -- 2.49.0