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Fri, 4 Sep 2026 14:54:26 -0500 From: Xiaogang.Chen To: CC: Xiaogang Chen Subject: [PATCH v2 4/4] drm/amdkfd: Apply AMDGPU_PTE_FRAG to pte of gart page table for THP mapping Date: Fri, 4 Sep 2026 14:54:21 -0500 Message-ID: <20260904195421.42919-5-xiaogang.chen@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260904195421.42919-1-xiaogang.chen@amd.com> References: <20260904195421.42919-1-xiaogang.chen@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: LV8PEPF00000066:EE_|SA0PR12MB4462:EE_ X-MS-Office365-Filtering-Correlation-Id: 85db3339-3b59-416c-96b7-08df0abe54f5 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|36860700016|82310400026|1800799024|376014|23010399003|56012099006|10067099003|11063799006|3023799007|22082099003|18002099003; X-Microsoft-Antispam-Message-Info: HNVA25I98502zlACOHZvliXdvqEKcD/vPDbN0n/c2tiGRuEKAQs+n4QEzOptN5SDpIUIOvpFOEIKb8P6X/Gp0b9p41PegKD3u9KtAAHQD9G1hYgvBJN+8Q5ovn4PKs29X8Zv9cqBEx3wlxfqA+2bgc+HaGErb0X1lc5HC8vpc9QLUXL9Ea16Ifpm1M0P8S/3NbvjJv++2uc1+KkZL3oLK34SmhnJaS8+kaR+ucADfNR4PAHGURwf6YM/x+KLhNhlHJDrKUvuoQG6Nu3KBRD1nEYFUtTWQOfTOZdB8JPCVsrz3fEhEp0uykBT2VlNlmUIiwawCSoHYyuh0fkMtKheqB1jZn6nXwtinvDmynJfBDikzQ63i5mbNDRGeS0vebE9pYYNMFQ81iei7rGxYypqoXJDsjyA0YCCVf5Z4iwfgCn8iALNNo+tiPDvWrDYBgUwtgByAzp+l7qYjWei/tIuA1K89EEGBttu0m5yWU611/DiVSGycPHjWWrecMM4FyTV9Jsz/gn6ucJgapZS+4GAk/Qj/IL3c1sxCb1b6ScMkXP8sex9rlF8xOm/QBKv51/Z04bb220UdntkAWxTEZf6kz7rrrqdfgoQzVePKYHhBQw3vtT+CtNziIn6Bd1GszyWgthkmOeEL8tmzcbkuT1HV3uJfWl2Kf/xJvmyrjvXJpOF6Oqv4dfeQdNrNm13MIr8H0ZoIiRtXv4YLYQER6FeDg== X-Forefront-Antispam-Report: CIP:165.204.84.17; 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Ip=[165.204.84.17]; Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: LV8PEPF00000066.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA0PR12MB4462 X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" From: Xiaogang Chen When both sys ram and vram are physical continuous HPAGE_PMD_NR pages during migration set AMDGPU_PTE_FRAG(HPAGE_PMD_ORDER) at pte in gart page table to let hardware know the migrating pages are HPAGE_PMD_NR size THP. That will reduce hardware TLB pressure or increase TLB hit ration. Signed-off-by: Xiaogang Chen --- drivers/gpu/drm/amd/amdkfd/kfd_migrate.c | 45 ++++++++++++++---------- 1 file changed, 27 insertions(+), 18 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c b/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c index af39e547c1fa..8a2fbe3a7613 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c @@ -48,7 +48,7 @@ static int svm_migrate_gart_map(struct amdgpu_ring *ring, struct amdgpu_ttm_buffer_entity *entity, u64 npages, - dma_addr_t *addr, u64 *gart_addr, u64 flags) + dma_addr_t *addr, u64 *gart_addr, u64 flags, bool is_thp) { struct amdgpu_device *adev = ring->adev; struct amdgpu_job *job; @@ -90,6 +90,9 @@ svm_migrate_gart_map(struct amdgpu_ring *ring, pte_flags |= AMDGPU_PTE_WRITEABLE; pte_flags |= adev->gart.gart_pte_flags; + if (is_thp) + pte_flags |= AMDGPU_PTE_FRAG(HPAGE_PMD_ORDER); + cpu_addr = &job->ibs[0].ptr[num_dw]; amdgpu_gart_map(adev, 0, npages, addr, pte_flags, cpu_addr); @@ -108,6 +111,7 @@ svm_migrate_gart_map(struct amdgpu_ring *ring, * @npages: number of pages to copy * @direction: enum MIGRATION_COPY_DIR * @mfence: output, sdma fence to signal after sdma is done + * @is_thp: both sys and vram are physical continuous HPAGE_PMD_NR pages * * ram address uses GART table continuous entries mapping to ram pages, * vram address uses direct mapping of vram pages, which must have npages @@ -126,7 +130,7 @@ static int svm_migrate_copy_memory_gart(struct amdgpu_device *adev, dma_addr_t *sys, u64 *vram, u64 npages, enum MIGRATION_COPY_DIR direction, - struct dma_fence **mfence) + struct dma_fence **mfence, bool is_thp) { const u64 GTT_MAX_PAGES = (AMDGPU_GTT_MAX_TRANSFER_SIZE >> PAGE_SHIFT); struct amdgpu_ring *ring; @@ -136,6 +140,12 @@ svm_migrate_copy_memory_gart(struct amdgpu_device *adev, dma_addr_t *sys, u64 size; int r = 0; + if (is_thp && npages != HPAGE_PMD_NR) { + dev_warn(adev->dev, "THP migration should have %d pages\n", + HPAGE_PMD_NR); + is_thp = false; + } + ring = to_amdgpu_ring(adev->mman.buffer_funcs_scheds[0]); entity = &adev->mman.move_entities[0]; @@ -146,11 +156,12 @@ svm_migrate_copy_memory_gart(struct amdgpu_device *adev, dma_addr_t *sys, if (direction == FROM_VRAM_TO_RAM) { gart_s = svm_migrate_direct_mapping_addr(adev, *vram); - r = svm_migrate_gart_map(ring, entity, size, sys, &gart_d, 0); + r = svm_migrate_gart_map(ring, entity, size, sys, &gart_d, 0, + is_thp); } else if (direction == FROM_RAM_TO_VRAM) { r = svm_migrate_gart_map(ring, entity, size, sys, &gart_s, - KFD_IOCTL_SVM_FLAG_GPU_RO); + KFD_IOCTL_SVM_FLAG_GPU_RO, is_thp); gart_d = svm_migrate_direct_mapping_addr(adev, *vram); } if (r) { @@ -362,7 +373,7 @@ svm_migrate_copy_to_vram(struct kfd_node *node, struct svm_range *prange, adev, src + i - j, dst + i - j, j, FROM_RAM_TO_VRAM, - mfence); + mfence, false); if (r) goto out_free_vram_pages; @@ -398,7 +409,7 @@ svm_migrate_copy_to_vram(struct kfd_node *node, struct svm_range *prange, adev, src + i, dst + i, HPAGE_PMD_NR, FROM_RAM_TO_VRAM, - mfence); + mfence, true); /* mark head page dma mapping as THP, tail pages dma addr * are set to 0 for following dma_unmap @@ -433,7 +444,7 @@ svm_migrate_copy_to_vram(struct kfd_node *node, struct svm_range *prange, adev, src + i - j, dst + i - j, j, FROM_RAM_TO_VRAM, - mfence); + mfence, false); if (r) goto out_free_vram_pages; @@ -452,7 +463,7 @@ svm_migrate_copy_to_vram(struct kfd_node *node, struct svm_range *prange, r = svm_migrate_copy_memory_gart(adev, src + i - j, dst + i - j, j, FROM_RAM_TO_VRAM, - mfence); + mfence, false); if (r) goto out_free_vram_pages; } @@ -466,7 +477,7 @@ svm_migrate_copy_to_vram(struct kfd_node *node, struct svm_range *prange, if (j > 0) r = svm_migrate_copy_memory_gart(adev, src + i - j, dst + i - j, j, - FROM_RAM_TO_VRAM, mfence); + FROM_RAM_TO_VRAM, mfence, false); out_free_vram_pages: if (r) { @@ -736,7 +747,7 @@ svm_migrate_copy_to_ram(struct amdgpu_device *adev, struct svm_range *prange, r = svm_migrate_copy_memory_gart(adev, dst + i - j, src + i - j, j, FROM_VRAM_TO_RAM, - mfence); + mfence, false); if (r) goto out_oom; j = 0; @@ -751,7 +762,7 @@ svm_migrate_copy_to_ram(struct amdgpu_device *adev, struct svm_range *prange, r = svm_migrate_copy_memory_gart(adev, dst + i - j, src + i - j, j, FROM_VRAM_TO_RAM, - mfence); + mfence, false); if (r) goto out_oom; j = 0; @@ -795,7 +806,8 @@ svm_migrate_copy_to_ram(struct amdgpu_device *adev, struct svm_range *prange, /* migrate previous accumulated pages */ if(j) { r = svm_migrate_copy_memory_gart(adev, dst + i - j, - src + i - j, j, FROM_VRAM_TO_RAM, mfence); + src + i - j, j, FROM_VRAM_TO_RAM, + mfence, false); if (r) goto out_oom; j = 0; @@ -809,14 +821,11 @@ svm_migrate_copy_to_ram(struct amdgpu_device *adev, struct svm_range *prange, } /* migrate the HPAGE_PMD_NR pages above */ - /* svm_migrate_copy_memory_gart will add a paramter to indicate - * the migration is for 2MB THP - */ r = svm_migrate_copy_memory_gart( adev, dst + i, src + i, HPAGE_PMD_NR, FROM_VRAM_TO_RAM, - mfence); + mfence, true); /* mark head page dma mapping as THP, tail pages dma addr * are set to 0 for following dma_unmap @@ -837,7 +846,7 @@ svm_migrate_copy_to_ram(struct amdgpu_device *adev, struct svm_range *prange, if (j > 0) r = svm_migrate_copy_memory_gart(adev, dst + i - j, src + i - j, j, - FROM_VRAM_TO_RAM, mfence); + FROM_VRAM_TO_RAM, mfence, false); out_oom: if (r) { pr_debug("failed %d copy to ram\n", r); @@ -1299,7 +1308,7 @@ int kgd2kfd_init_zone_device(struct amdgpu_device *adev) amdgpu_amdkfd_reserve_system_mem(SVM_HMM_PAGE_STRUCT_SIZE(size)); - pr_info("---XCHEN 3.2 HMM registered %ldMB device memory\n", size >> 20); + pr_info("HMM registered %ldMB device memory\n", size >> 20); return 0; } -- 2.34.1