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[79.129.254.8]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-48594172546sm22191354f8f.15.2026.09.07.13.33.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Sep 2026 13:33:37 -0700 (PDT) From: =?UTF-8?q?Timur=20Krist=C3=B3f?= To: amd-gfx@lists.freedesktop.org, =?UTF-8?q?Marek=20Ol=C5=A1=C3=A1k?= , Alex Deucher , =?UTF-8?q?Christian=20K=C3=B6nig?= , Tvrtko Ursulin , pierre-eric.pelloux-prayer@amd.com, Natalie Vock , Lijo Lazar , Felix Kuehling Cc: =?UTF-8?q?Timur=20Krist=C3=B3f?= Subject: [PATCH 02/12] drm/amdgpu/sdma: Refactor SI DMA clock gating functions to be per-instance Date: Mon, 7 Sep 2026 22:33:06 +0200 Message-ID: <20260907203316.159103-3-timur.kristof@gmail.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260907203316.159103-1-timur.kristof@gmail.com> References: <20260907203316.159103-1-timur.kristof@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" Refactor clock gating functions to take the SDMA engine instance ID as an argument and only affect one SDMA engine instance at once. Signed-off-by: Timur Kristóf --- drivers/gpu/drm/amd/amdgpu/si_dma.c | 63 +++++++++++++---------------- 1 file changed, 29 insertions(+), 34 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/si_dma.c b/drivers/gpu/drm/amd/amdgpu/si_dma.c index 483a0cfb7c8f..fa67415acbc4 100644 --- a/drivers/gpu/drm/amd/amdgpu/si_dma.c +++ b/drivers/gpu/drm/amd/amdgpu/si_dma.c @@ -654,45 +654,40 @@ static int si_dma_process_trap_irq(struct amdgpu_device *adev, return 0; } -static int si_dma_set_clockgating_state(struct amdgpu_ip_block *ip_block, - enum amd_clockgating_state state) +static void si_dma_enable_mgcg(struct amdgpu_device *adev, + const u32 instance_id, + const bool enable) { - u32 orig, data, offset; - int i; - bool enable; - struct amdgpu_device *adev = ip_block->adev; - - enable = (state == AMD_CG_STATE_GATE); + const u32 reg_offset = sdma_offsets[instance_id]; + u32 orig, data; if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) { - for (i = 0; i < adev->sdma.num_instances; i++) { - if (i == 0) - offset = DMA0_REGISTER_OFFSET; - else - offset = DMA1_REGISTER_OFFSET; - orig = data = RREG32(mmDMA_POWER_CNTL + offset); - data &= ~DMA_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; - if (data != orig) - WREG32(mmDMA_POWER_CNTL + offset, data); - WREG32(mmDMA_CLK_CTRL + offset, 0x00000100); - } + orig = data = RREG32(mmDMA_POWER_CNTL + reg_offset); + data &= ~DMA_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; + if (data != orig) + WREG32(mmDMA_POWER_CNTL + reg_offset, data); + WREG32(mmDMA_CLK_CTRL + reg_offset, 0x00000100); } else { - for (i = 0; i < adev->sdma.num_instances; i++) { - if (i == 0) - offset = DMA0_REGISTER_OFFSET; - else - offset = DMA1_REGISTER_OFFSET; - orig = data = RREG32(mmDMA_POWER_CNTL + offset); - data |= DMA_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; - if (data != orig) - WREG32(mmDMA_POWER_CNTL + offset, data); - - orig = data = RREG32(mmDMA_CLK_CTRL + offset); - data = 0xff000000; - if (data != orig) - WREG32(mmDMA_CLK_CTRL + offset, data); - } + orig = data = RREG32(mmDMA_POWER_CNTL + reg_offset); + data |= DMA_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; + if (data != orig) + WREG32(mmDMA_POWER_CNTL + reg_offset, data); + + orig = data = RREG32(mmDMA_CLK_CTRL + reg_offset); + data = 0xff000000; + if (data != orig) + WREG32(mmDMA_CLK_CTRL + reg_offset, data); } +} + +static int si_dma_set_clockgating_state(struct amdgpu_ip_block *const ip_block, + const enum amd_clockgating_state state) +{ + struct amdgpu_device *const adev = ip_block->adev; + int i; + + for (i = 0; i < adev->sdma.num_instances; i++) + si_dma_enable_mgcg(adev, i, state == AMD_CG_STATE_GATE); return 0; } -- 2.55.0