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[79.129.254.8]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-48594172546sm22191354f8f.15.2026.09.07.13.33.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Sep 2026 13:33:53 -0700 (PDT) From: =?UTF-8?q?Timur=20Krist=C3=B3f?= To: amd-gfx@lists.freedesktop.org, =?UTF-8?q?Marek=20Ol=C5=A1=C3=A1k?= , Alex Deucher , =?UTF-8?q?Christian=20K=C3=B6nig?= , Tvrtko Ursulin , pierre-eric.pelloux-prayer@amd.com, Natalie Vock , Lijo Lazar , Felix Kuehling Cc: =?UTF-8?q?Timur=20Krist=C3=B3f?= Subject: [PATCH 08/12] drm/amdgpu/sdma: Refactor SDMA v3.0 clock gating functions to be per-instance Date: Mon, 7 Sep 2026 22:33:12 +0200 Message-ID: <20260907203316.159103-9-timur.kristof@gmail.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260907203316.159103-1-timur.kristof@gmail.com> References: <20260907203316.159103-1-timur.kristof@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" Refactor clock gating functions to take the SDMA engine instance ID as an argument and only affect one SDMA engine instance at once. Signed-off-by: Timur Kristóf --- drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 81 +++++++++++++------------- 1 file changed, 39 insertions(+), 42 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c index 6213a0c77590..3d0f94372e04 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c @@ -1345,66 +1345,60 @@ static int sdma_v3_0_process_illegal_inst_irq(struct amdgpu_device *adev, static void sdma_v3_0_update_sdma_medium_grain_clock_gating( struct amdgpu_device *adev, - bool enable) + const u32 instance_id, + const bool enable) { + const u32 reg_offset = sdma_offsets[instance_id]; uint32_t temp, data; - int i; if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) { - for (i = 0; i < adev->sdma.num_instances; i++) { - temp = data = RREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i]); - data &= ~(SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK | - SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK | - SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK | - SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK | - SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK | - SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK | - SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK | - SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK); - if (data != temp) - WREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i], data); - } - } else { - for (i = 0; i < adev->sdma.num_instances; i++) { - temp = data = RREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i]); - data |= SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK | + temp = data = RREG32(mmSDMA0_CLK_CTRL + reg_offset); + data &= ~(SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK | SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK | SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK | SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK | SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK | SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK | SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK | - SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK; - - if (data != temp) - WREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i], data); - } + SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK); + if (data != temp) + WREG32(mmSDMA0_CLK_CTRL + reg_offset, data); + } else { + temp = data = RREG32(mmSDMA0_CLK_CTRL + reg_offset); + data |= SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK | + SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK | + SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK | + SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK | + SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK | + SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK | + SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK | + SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK; + + if (data != temp) + WREG32(mmSDMA0_CLK_CTRL + reg_offset, data); } } static void sdma_v3_0_update_sdma_medium_grain_light_sleep( struct amdgpu_device *adev, - bool enable) + const u32 instance_id, + const bool enable) { + const u32 reg_offset = sdma_offsets[instance_id]; uint32_t temp, data; - int i; if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) { - for (i = 0; i < adev->sdma.num_instances; i++) { - temp = data = RREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i]); - data |= SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; + temp = data = RREG32(mmSDMA0_POWER_CNTL + reg_offset); + data |= SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; - if (temp != data) - WREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i], data); - } + if (temp != data) + WREG32(mmSDMA0_POWER_CNTL + reg_offset, data); } else { - for (i = 0; i < adev->sdma.num_instances; i++) { - temp = data = RREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i]); - data &= ~SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; + temp = data = RREG32(mmSDMA0_POWER_CNTL + reg_offset); + data &= ~SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; - if (temp != data) - WREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i], data); - } + if (temp != data) + WREG32(mmSDMA0_POWER_CNTL + reg_offset, data); } } @@ -1412,6 +1406,7 @@ static int sdma_v3_0_set_clockgating_state(struct amdgpu_ip_block *ip_block, enum amd_clockgating_state state) { struct amdgpu_device *adev = ip_block->adev; + int i; if (amdgpu_sriov_vf(adev)) return 0; @@ -1420,10 +1415,12 @@ static int sdma_v3_0_set_clockgating_state(struct amdgpu_ip_block *ip_block, case CHIP_FIJI: case CHIP_CARRIZO: case CHIP_STONEY: - sdma_v3_0_update_sdma_medium_grain_clock_gating(adev, - state == AMD_CG_STATE_GATE); - sdma_v3_0_update_sdma_medium_grain_light_sleep(adev, - state == AMD_CG_STATE_GATE); + for (i = 0; i < adev->sdma.num_instances; i++) { + sdma_v3_0_update_sdma_medium_grain_clock_gating( + adev, i, state == AMD_CG_STATE_GATE); + sdma_v3_0_update_sdma_medium_grain_light_sleep( + adev, i, state == AMD_CG_STATE_GATE); + } break; default: break; -- 2.55.0