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Tue, 8 Sep 2026 06:36:09 -0500 From: Chenyu Chen To: CC: Harry Wentland , Leo Li , Aurabindo Pillai , Roman Li , Wayne Lin , Tom Chung , "Fangzhi Zuo" , Dan Wheeler , Ray Wu , Ivan Lipski , Alex Hung , James Lin , Chenyu Chen , Bhawanpreet Lakha , "Chenyu Chen" Subject: [PATCH 17/66] drm/amd/display: Test optional plane property creation Date: Tue, 8 Sep 2026 19:31:10 +0800 Message-ID: <20260908113338.2433445-18-chen-yu.chen@amd.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260908113338.2433445-1-chen-yu.chen@amd.com> References: <20260908113338.2433445-1-chen-yu.chen@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF00002326:EE_|SJ2PR12MB8977:EE_ X-MS-Office365-Filtering-Correlation-Id: 1a525af5-8690-4db3-d6a6-08df0d9d6670 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|23010399003|36860700016|1800799024|82310400026|376014|6133799003|10067099003|18002099003|22082099003|56012099006|11063799006|5023799004; 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DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 2wtVhy25hgeIk2yIlknAZVdB2MJPjyrxJcBYBUGLGS5ctX1cuJmlYpiP/OSZgMob+pQr8KL8HeOdXrdGfxp/K4fUmE7GsFvHjZV7zfZ47U8rsqM7pWCvAdRwTmaZ4mkUPvE3DJ6REEjqLrOzdWUcIHXXYnH7HXrp6mx73GgPE9caJttC/wYF7x2LFg3iEgV08gc+B3pMTHO46GBxOghpk1IIQf2c1bOtNT6iDRPWkOMJ7UX47i1kPFzlXk501kCyOKq+bSxGPScyiDse7nc1vnHF7q1Cg0GMvZMUwVQx4ZqIIEgY+5EnPSbrpr329QA8+NahqY/6Rhwn1gEh07I8BLWe8VnPQr2xN944IXnRn/b0UeBZqP6gPYhWW1K5H3rqG6UNtc30Q3rsx5QW7mRemo8uaGaIHvXGYtaA6DsyzaG/UDlEcOzsBhxOItHXX2j/ X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Sep 2026 11:36:18.8308 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1a525af5-8690-4db3-d6a6-08df0d9d6670 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[satlexmb08.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF00002326.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ2PR12MB8977 X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" From: Alex Hung [WHAT] Add KUnit tests for amdgpu_dm_plane_init() covering the rotation property and framebuffer damage clips on newer ASICs, and the default color pipeline on DCN 3.0 and newer. [HOW] Initialize an overlay plane on a standard DRM KUnit device, varying the ASIC type, the DCE IP version and the DC context DCE version to select each optional property. Assisted-by: Copilot:Claude-Opus-5 Reviewed-by: Bhawanpreet Lakha Signed-off-by: Alex Hung Signed-off-by: Chenyu Chen --- .../amd/display/amdgpu_dm/amdgpu_dm_plane.c | 1 + .../amdgpu_dm/tests/amdgpu_dm_plane_test.c | 70 +++++++++++++++++++ 2 files changed, 71 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c index 0a5a7347238e..23054952a6f6 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c @@ -2294,6 +2294,7 @@ int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm, return 0; } +EXPORT_IF_KUNIT(amdgpu_dm_plane_init); bool amdgpu_dm_plane_is_video_format(uint32_t format) { diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_plane_test.c b/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_plane_test.c index 20826691b55d..a39c0acad6f7 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_plane_test.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_plane_test.c @@ -3941,6 +3941,73 @@ static void dm_test_panic_flush_disables_dcc(struct kunit *test) KUNIT_EXPECT_EQ(test, dm_test_clear_dcc_tiling_count, 1); } +/* + * Build a DM ready to initialize planes on a real DRM device. The plane itself + * is plain kzalloc'd because DRM frees it through drm_plane_helper_destroy() + * when the mode config is torn down. + */ +static struct drm_plane *dm_test_alloc_init_plane(struct kunit *test, + struct amdgpu_device **adev_out) +{ + struct amdgpu_device *adev; + struct drm_plane *plane; + + adev = dm_kunit_alloc_adev(test); + adev->family = AMDGPU_FAMILY_NV; + adev->dm.adev = adev; + adev->dm.dc = dm_kunit_alloc_dc_with_ctx(test); + + plane = kzalloc_obj(*plane, GFP_KERNEL); + KUNIT_ASSERT_NOT_NULL(test, plane); + plane->type = DRM_PLANE_TYPE_OVERLAY; + + *adev_out = adev; + + return plane; +} + +/** + * dm_test_plane_init_creates_optional_properties() - Verify optional properties. + * @test: KUnit test context. + * + * Verify if a Bonaire-or-newer non-cursor plane on a DCE version above 3.0.1 + * gains the rotation property and framebuffer damage clips. + */ +static void dm_test_plane_init_creates_optional_properties(struct kunit *test) +{ + struct amdgpu_device *adev; + struct drm_plane *plane; + + plane = dm_test_alloc_init_plane(test, &adev); + adev->asic_type = CHIP_BONAIRE; + adev->ip_versions[DCE_HWIP][0] = IP_VERSION(3, 1, 0); + + KUNIT_ASSERT_EQ(test, amdgpu_dm_plane_init(&adev->dm, plane, 1, NULL), 0); + + KUNIT_EXPECT_NOT_NULL(test, plane->rotation_property); + KUNIT_EXPECT_NOT_NULL(test, adev->ddev.mode_config.prop_fb_damage_clips); +} + +/** + * dm_test_plane_init_creates_color_pipeline() - Verify color pipeline creation. + * @test: KUnit test context. + * + * Verify if a non-cursor plane on DCN 3.0 or newer gets a default color + * pipeline exposed through the COLOR_PIPELINE property. + */ +static void dm_test_plane_init_creates_color_pipeline(struct kunit *test) +{ + struct amdgpu_device *adev; + struct drm_plane *plane; + + plane = dm_test_alloc_init_plane(test, &adev); + adev->dm.dc->ctx->dce_version = DCN_VERSION_3_0; + + KUNIT_ASSERT_EQ(test, amdgpu_dm_plane_init(&adev->dm, plane, 1, NULL), 0); + + KUNIT_EXPECT_NOT_NULL(test, plane->color_pipeline_property); +} + static struct kunit_case amdgpu_dm_plane_test_cases[] = { /* amdgpu_dm_plane_is_video_format() */ KUNIT_CASE(dm_test_plane_is_video_format_known_video), @@ -4078,6 +4145,9 @@ static struct kunit_case amdgpu_dm_plane_test_cases[] = { KUNIT_CASE(dm_test_validate_dcc_not_capable_fails), KUNIT_CASE(dm_test_validate_dcc_success_and_scan_mapping), KUNIT_CASE(dm_test_validate_dcc_independent_64b_mismatch_fails), + /* amdgpu_dm_plane_init() */ + KUNIT_CASE(dm_test_plane_init_creates_optional_properties), + KUNIT_CASE(dm_test_plane_init_creates_color_pipeline), {} }; -- 2.43.0