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Tue, 8 Sep 2026 06:37:29 -0500 From: Chenyu Chen To: CC: Harry Wentland , Leo Li , Aurabindo Pillai , Roman Li , Wayne Lin , Tom Chung , "Fangzhi Zuo" , Dan Wheeler , Ray Wu , Ivan Lipski , Alex Hung , James Lin , Chenyu Chen , Bhawanpreet Lakha , "Chenyu Chen" Subject: [PATCH 26/66] drm/amd/display: Test FRL bandwidth lookup Date: Tue, 8 Sep 2026 19:31:19 +0800 Message-ID: <20260908113338.2433445-27-chen-yu.chen@amd.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260908113338.2433445-1-chen-yu.chen@amd.com> References: <20260908113338.2433445-1-chen-yu.chen@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN2PEPF0000A895:EE_|SJ0PR12MB8166:EE_ X-MS-Office365-Filtering-Correlation-Id: 1a869db2-9061-4e97-0527-08df0d9d95cf X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|376014|23010399003|82310400026|1800799024|36860700016|6133799003|10067099003|56012099006|11063799006|3023799007|18002099003|22082099003; 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DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: /ERK7IfcQUJLskOMu5IkI0A9+gfRTDpokmc6uGE3My4gM+tH7HkviOMww2D3o/Kr/3QEklEBWLSWaOCANPNljkp+Ae5NuFSZwI6823R5J61xEG/bhVd82rIyy1CnsDyNpkU5IIY7VnfB/mzuKFKAJdJHVe3gV/MQu2avhBhn4vjE3neZfjyHHoXFIUfylss2dA27Gve82Z2Y3NSXCPzb5okxBbUPBbH48dcjBVAyXWJHtHDwwAzcFwyYY60Qqt7p6PRKC8SSA7zaVQWnZuiPFEycJAtc/S0EgMi37XWCUiAv+FyUWIsDlLMH8bgurqEki9RfbC5VfN1spMR1WHbf7guXuWOahFrDJdHJR5A5Lgx8yexCg5/2qgEXxF68Vz999OA9wk7j6J0lG6nhjuHTshsirZ2sMjouFZEW8fhnoRjGAMssrTSR4g7QYl17RrSI X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Sep 2026 11:37:38.3851 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1a869db2-9061-4e97-0527-08df0d9d95cf X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN2PEPF0000A895.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ0PR12MB8166 X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" From: Alex Hung [WHAT] Add KUnit tests for get_conv_frl_bw() covering a protocol converter without FRL support, a downstream port that is not HDMI, a sink whose maximum FRL rate is zero and the case where the converter rate is the bottleneck. [HOW] Populate the display info and the downstream port capabilities of the connector for each case and check both the returned verdict and the bandwidth values it reports. Assisted-by: Copilot:Claude-Opus-5 Reviewed-by: Bhawanpreet Lakha Signed-off-by: Alex Hung Signed-off-by: Chenyu Chen --- .../display/amdgpu_dm/amdgpu_dm_mst_types.c | 5 +- .../display/amdgpu_dm/amdgpu_dm_mst_types.h | 2 + .../tests/amdgpu_dm_mst_types_test.c | 135 ++++++++++++++++++ 3 files changed, 140 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c index cb202b28a37c..4c6e7c28e4f8 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c @@ -1231,8 +1231,8 @@ static int try_disable_dsc(struct drm_atomic_commit *state, return 0; } -static bool get_conv_frl_bw(struct amdgpu_dm_connector *aconnector, - uint32_t *bw_in_kbps, uint32_t *dsc_bw_in_kbps) +STATIC_IFN_KUNIT bool get_conv_frl_bw(struct amdgpu_dm_connector *aconnector, + uint32_t *bw_in_kbps, uint32_t *dsc_bw_in_kbps) { unsigned int max_conv_bw_in_kbps = 0; unsigned int max_sink_bw_in_kbps = 0; @@ -1258,6 +1258,7 @@ static bool get_conv_frl_bw(struct amdgpu_dm_connector *aconnector, return *bw_in_kbps > 0; // Frl endpoint is detected } +EXPORT_IF_KUNIT(get_conv_frl_bw); static void build_frl_mst_dsc_params(struct amdgpu_dm_connector *aconnector, struct dc_stream_state *stream, diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.h index 76db9a8330e5..e1a25afb570c 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.h @@ -107,6 +107,8 @@ enum dc_status dm_dp_mst_is_port_support_mode( void amdgpu_dm_mst_reset_mst_connector_setting(struct amdgpu_dm_connector *aconnector); bool is_synaptics_cascaded_panamera(struct dc_link *link, struct drm_dp_mst_port *port); bool dp_get_link_current_set_bw(struct drm_dp_aux *aux, uint32_t *cur_link_bw); +bool get_conv_frl_bw(struct amdgpu_dm_connector *aconnector, + uint32_t *bw_in_kbps, uint32_t *dsc_bw_in_kbps); bool validate_dsc_caps_on_connector(struct amdgpu_dm_connector *aconnector); bool retrieve_downstream_port_device(struct amdgpu_dm_connector *aconnector); bool retrieve_branch_specific_data(struct amdgpu_dm_connector *aconnector); diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_mst_types_test.c b/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_mst_types_test.c index 13c141d9963a..0e5dd4ca9aed 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_mst_types_test.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_mst_types_test.c @@ -2979,6 +2979,136 @@ static void dm_mst_test_port_mode_branch_throughput_exceeded(struct kunit *test) DC_FAIL_BANDWIDTH_VALIDATE); } +/* Tests for get_conv_frl_bw */ + +/* Deterministic stand-in for the DC raw-FRL-rate lookup table. */ +static uint32_t dm_mst_test_bw_kbps_from_raw_frl(uint8_t bw) +{ + return bw * 3000; +} + +/* + * Wire up a DP-to-HDMI2.1 protocol converter: the PCON capability lives on the + * DC caps, the converter's own limit in the downstream port caps, and the sink + * limits in the EDID caps. + */ +static struct amdgpu_dm_connector *dm_mst_test_alloc_frl_connector(struct kunit *test, + bool pcon_support, + u8 dwn_strm_port_type, + u8 max_encoded_link_bw, + u8 max_frl_rate, + u8 frl_dsc_max_frl_rate) +{ + struct amdgpu_dm_connector *aconnector; + struct link_service *link_srv; + struct dc_sink *sink; + struct dc_link *link; + struct dc *dc; + + aconnector = kunit_kzalloc(test, sizeof(*aconnector), GFP_KERNEL); + sink = kunit_kzalloc(test, sizeof(*sink), GFP_KERNEL); + link_srv = kunit_kzalloc(test, sizeof(*link_srv), GFP_KERNEL); + KUNIT_ASSERT_NOT_NULL(test, aconnector); + KUNIT_ASSERT_NOT_NULL(test, sink); + KUNIT_ASSERT_NOT_NULL(test, link_srv); + + link_srv->bw_kbps_from_raw_frl_link_rate_data = dm_mst_test_bw_kbps_from_raw_frl; + + dc = dm_kunit_alloc_dc_with_ctx(test); + dc->link_srv = link_srv; + dc->caps.dp_hdmi21_pcon_support = pcon_support; + + link = dm_kunit_alloc_link(test); + link->dc = dc; + + sink->edid_caps.max_frl_rate = max_frl_rate; + sink->edid_caps.frl_dsc_max_frl_rate = frl_dsc_max_frl_rate; + + aconnector->dc_link = link; + aconnector->dc_sink = sink; + aconnector->mst_downstream_port_caps.bytes.byte0.bits.DWN_STRM_PORTX_TYPE = + dwn_strm_port_type; + aconnector->mst_downstream_port_caps.bytes.byte2.bits.MAX_ENCODED_LINK_BW_SUPPORT = + max_encoded_link_bw; + + return aconnector; +} + +/** + * dm_mst_test_conv_frl_bw_no_pcon_support - DC without PCON support finds no FRL + * @test: KUnit test context + */ +static void dm_mst_test_conv_frl_bw_no_pcon_support(struct kunit *test) +{ + struct amdgpu_dm_connector *aconnector; + uint32_t bw_in_kbps = 0; + uint32_t dsc_bw_in_kbps = 0; + + aconnector = dm_mst_test_alloc_frl_connector(test, false, DOWN_STREAM_DETAILED_HDMI, + 3, 5, 2); + + KUNIT_EXPECT_FALSE(test, get_conv_frl_bw(aconnector, &bw_in_kbps, &dsc_bw_in_kbps)); + KUNIT_EXPECT_EQ(test, bw_in_kbps, 0U); + KUNIT_EXPECT_EQ(test, dsc_bw_in_kbps, 0U); +} + +/** + * dm_mst_test_conv_frl_bw_not_hdmi_port - a non-HDMI downstream port has no FRL + * @test: KUnit test context + */ +static void dm_mst_test_conv_frl_bw_not_hdmi_port(struct kunit *test) +{ + struct amdgpu_dm_connector *aconnector; + uint32_t bw_in_kbps = 0; + uint32_t dsc_bw_in_kbps = 0; + + aconnector = dm_mst_test_alloc_frl_connector(test, true, DOWN_STREAM_DETAILED_DP, 3, 5, 2); + + KUNIT_EXPECT_FALSE(test, get_conv_frl_bw(aconnector, &bw_in_kbps, &dsc_bw_in_kbps)); + KUNIT_EXPECT_EQ(test, bw_in_kbps, 0U); +} + +/** + * dm_mst_test_conv_frl_bw_sink_without_frl - a sink not reporting FRL is skipped + * @test: KUnit test context + * + * Without a sink FRL rate in the EDID there is no endpoint to negotiate with, + * so no bandwidth is reported even though the converter advertises one. + */ +static void dm_mst_test_conv_frl_bw_sink_without_frl(struct kunit *test) +{ + struct amdgpu_dm_connector *aconnector; + uint32_t bw_in_kbps = 0; + uint32_t dsc_bw_in_kbps = 0; + + aconnector = dm_mst_test_alloc_frl_connector(test, true, DOWN_STREAM_DETAILED_HDMI, + 3, 0, 2); + + KUNIT_EXPECT_FALSE(test, get_conv_frl_bw(aconnector, &bw_in_kbps, &dsc_bw_in_kbps)); + KUNIT_EXPECT_EQ(test, bw_in_kbps, 0U); +} + +/** + * dm_mst_test_conv_frl_bw_bottleneck - the converter and sink limits are combined + * @test: KUnit test context + * + * The reported bandwidth is the smaller of the converter and sink FRL rates, + * and the DSC bandwidth is further capped by the sink's DSC FRL rate. + */ +static void dm_mst_test_conv_frl_bw_bottleneck(struct kunit *test) +{ + struct amdgpu_dm_connector *aconnector; + uint32_t bw_in_kbps = 0; + uint32_t dsc_bw_in_kbps = 0; + + aconnector = dm_mst_test_alloc_frl_connector(test, true, DOWN_STREAM_DETAILED_HDMI, + 3, 5, 2); + + KUNIT_EXPECT_TRUE(test, get_conv_frl_bw(aconnector, &bw_in_kbps, &dsc_bw_in_kbps)); + KUNIT_EXPECT_EQ(test, bw_in_kbps, 9000U); + KUNIT_EXPECT_EQ(test, dsc_bw_in_kbps, 6000U); +} + static struct kunit_case dm_mst_types_test_cases[] = { /* needs_dsc_aux_workaround tests */ KUNIT_CASE(dm_mst_test_needs_dsc_aux_workaround_match), @@ -3084,6 +3214,11 @@ static struct kunit_case dm_mst_types_test_cases[] = { KUNIT_CASE(dm_mst_test_port_mode_last_link_synaptics_quirk), KUNIT_CASE(dm_mst_test_port_mode_upstream_vc_too_small), KUNIT_CASE(dm_mst_test_port_mode_branch_throughput_exceeded), + /* get_conv_frl_bw tests */ + KUNIT_CASE(dm_mst_test_conv_frl_bw_no_pcon_support), + KUNIT_CASE(dm_mst_test_conv_frl_bw_not_hdmi_port), + KUNIT_CASE(dm_mst_test_conv_frl_bw_sink_without_frl), + KUNIT_CASE(dm_mst_test_conv_frl_bw_bottleneck), {} }; -- 2.43.0