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Ip=[165.204.84.17]; Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN7PEPF0000009C.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS7PR12MB6071 X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" From: Alvin Lee [Description] - DCC register is latched on the surface address register being updated - In this case couple the DCC programming and the address update together to ensure the DCC programming is always taken as expected - Update address programming function to take in DCC bool, use for DCN6+ and leave older DCN unchanged. Reviewed-by: Dillon Varone Signed-off-by: Alvin Lee Signed-off-by: Chenyu Chen --- .../drm/amd/display/dc/core/dc_hw_sequencer.c | 4 ++- .../amd/display/dc/hubp/dcn10/dcn10_hubp.c | 4 ++- .../amd/display/dc/hubp/dcn10/dcn10_hubp.h | 3 +- .../amd/display/dc/hubp/dcn20/dcn20_hubp.c | 5 +++- .../amd/display/dc/hubp/dcn20/dcn20_hubp.h | 3 +- .../amd/display/dc/hubp/dcn21/dcn21_hubp.c | 5 +++- .../amd/display/dc/hubp/dcn30/dcn30_hubp.c | 5 +++- .../amd/display/dc/hubp/dcn30/dcn30_hubp.h | 3 +- .../amd/display/dc/hubp/dcn401/dcn401_hubp.c | 5 +++- .../amd/display/dc/hubp/dcn401/dcn401_hubp.h | 3 +- .../amd/display/dc/hubp/dcn42/dcn42_hubp.c | 5 +++- .../amd/display/dc/hubp/dcn50/dcn50_hubp.c | 28 ++++++++++++------- .../amd/display/dc/hubp/dcn50/dcn50_hubp.h | 3 +- .../amd/display/dc/hwss/dcn10/dcn10_hwseq.c | 6 ++-- .../amd/display/dc/hwss/dcn20/dcn20_hwseq.c | 3 +- .../amd/display/dc/hwss/dcn201/dcn201_hwseq.c | 3 +- .../drm/amd/display/dc/hwss/hw_sequencer.h | 1 + drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h | 3 +- 18 files changed, 65 insertions(+), 27 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c index ccc58d42e0ab..6ed22b2e9c74 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c @@ -1713,7 +1713,8 @@ void hwss_execute_sequence(struct dc *dc, params->update_plane_addr_params.hubp->funcs->hubp_program_surface_flip_and_addr( params->update_plane_addr_params.hubp, ¶ms->update_plane_addr_params.address, - params->update_plane_addr_params.flip_immediate); + params->update_plane_addr_params.flip_immediate, + params->update_plane_addr_params.dcc); break; case DPP_SET_INPUT_TRANSFER_FUNC: hws->funcs.set_input_transfer_func(¶ms->set_input_transfer_func_params); @@ -2356,6 +2357,7 @@ void hwss_add_hubp_update_plane_addr(struct block_sequence_state *seq_state, dc->hwss.prepare_plane_addr_update(dc, pipe_ctx, ¶ms->address, ¶ms->flip_immediate); params->hubp = hubp; + params->dcc = pipe_ctx->plane_state ? pipe_ctx->plane_state->dcc.enable : false; seq_state->steps[*seq_state->num_steps].func = HUBP_UPDATE_PLANE_ADDR; (*seq_state->num_steps)++; } diff --git a/drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c b/drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c index d8eb5996b577..2a4be0c7a724 100644 --- a/drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c +++ b/drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c @@ -350,10 +350,12 @@ void hubp1_program_pixel_format( bool hubp1_program_surface_flip_and_addr( struct hubp *hubp, const struct dc_plane_address *address, - bool flip_immediate) + bool flip_immediate, + bool dcc) { struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); + (void)dcc; //program flip type REG_UPDATE(DCSURF_FLIP_CONTROL, diff --git a/drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h b/drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h index f2571076fc50..0c1d5e518f97 100644 --- a/drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h +++ b/drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h @@ -905,7 +905,8 @@ void hubp_reset(struct hubp *hubp); bool hubp1_program_surface_flip_and_addr( struct hubp *hubp, const struct dc_plane_address *address, - bool flip_immediate); + bool flip_immediate, + bool dcc); bool hubp1_is_flip_pending(struct hubp *hubp); diff --git a/drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c b/drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c index cf2c9f80056e..79a429814061 100644 --- a/drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c +++ b/drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c @@ -730,10 +730,13 @@ bool hubp2_dmdata_status_done(struct hubp *hubp) bool hubp2_program_surface_flip_and_addr( struct hubp *hubp, const struct dc_plane_address *address, - bool flip_immediate) + bool flip_immediate, + bool dcc) { struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); + (void)dcc; + //program flip type REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_FLIP_TYPE, flip_immediate); diff --git a/drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h b/drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h index ea90dee05d5f..3ae06bf89f79 100644 --- a/drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h +++ b/drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h @@ -399,7 +399,8 @@ void hubp2_program_deadline( bool hubp2_program_surface_flip_and_addr( struct hubp *hubp, const struct dc_plane_address *address, - bool flip_immediate); + bool flip_immediate, + bool dcc); void hubp2_dcc_control(struct hubp *hubp, bool enable, enum hubp_ind_block_size independent_64b_blks); diff --git a/drivers/gpu/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c b/drivers/gpu/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c index 0dba8ff8a19d..c667db319baf 100644 --- a/drivers/gpu/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c +++ b/drivers/gpu/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c @@ -696,10 +696,13 @@ static void dmcub_PLAT_54186_wa(struct hubp *hubp, static bool hubp21_program_surface_flip_and_addr( struct hubp *hubp, const struct dc_plane_address *address, - bool flip_immediate) + bool flip_immediate, + bool dcc) { struct surface_flip_registers flip_regs = { 0 }; + (void)dcc; + flip_regs.vmid = address->vmid; switch (address->type) { diff --git a/drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c b/drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c index 4f5f10f6d1cc..72698b5cf5f7 100644 --- a/drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c +++ b/drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c @@ -68,10 +68,13 @@ void hubp3_set_vm_system_aperture_settings(struct hubp *hubp, bool hubp3_program_surface_flip_and_addr( struct hubp *hubp, const struct dc_plane_address *address, - bool flip_immediate) + bool flip_immediate, + bool dcc) { struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); + (void)dcc; + //program flip type REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_FLIP_TYPE, flip_immediate); diff --git a/drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h b/drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h index c767e9f4f9b3..faa7e0379f4e 100644 --- a/drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h +++ b/drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.h @@ -260,7 +260,8 @@ void hubp3_set_vm_system_aperture_settings(struct hubp *hubp, bool hubp3_program_surface_flip_and_addr( struct hubp *hubp, const struct dc_plane_address *address, - bool flip_immediate); + bool flip_immediate, + bool dcc); void hubp3_program_surface_config( struct hubp *hubp, diff --git a/drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c b/drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c index 2acdac35a382..5ca40941c355 100644 --- a/drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c +++ b/drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c @@ -486,10 +486,13 @@ void hubp401_setup_interdependent( bool hubp401_program_surface_flip_and_addr( struct hubp *hubp, const struct dc_plane_address *address, - bool flip_immediate) + bool flip_immediate, + bool dcc) { struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); + (void)dcc; + //program flip type REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_FLIP_TYPE, flip_immediate); diff --git a/drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h b/drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h index adf343837652..818cea479272 100644 --- a/drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h +++ b/drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h @@ -271,7 +271,8 @@ void hubp401_setup_interdependent( bool hubp401_program_surface_flip_and_addr( struct hubp *hubp, const struct dc_plane_address *address, - bool flip_immediate); + bool flip_immediate, + bool dcc); void hubp401_dcc_control(struct hubp *hubp, struct dc_plane_dcc_param *dcc); diff --git a/drivers/gpu/drm/amd/display/dc/hubp/dcn42/dcn42_hubp.c b/drivers/gpu/drm/amd/display/dc/hubp/dcn42/dcn42_hubp.c index 96d3310e2c3f..0c8a23cef1e0 100644 --- a/drivers/gpu/drm/amd/display/dc/hubp/dcn42/dcn42_hubp.c +++ b/drivers/gpu/drm/amd/display/dc/hubp/dcn42/dcn42_hubp.c @@ -398,10 +398,13 @@ void hubp42_program_3dlut_fl_config(struct hubp *hubp, static bool hubp42_program_surface_flip_and_addr( struct hubp *hubp, const struct dc_plane_address *address, - bool flip_immediate) + bool flip_immediate, + bool dcc) { struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); + (void)dcc; + //program flip type REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_FLIP_TYPE, flip_immediate); diff --git a/drivers/gpu/drm/amd/display/dc/hubp/dcn50/dcn50_hubp.c b/drivers/gpu/drm/amd/display/dc/hubp/dcn50/dcn50_hubp.c index 0230f03590cf..ba86e30b1180 100644 --- a/drivers/gpu/drm/amd/display/dc/hubp/dcn50/dcn50_hubp.c +++ b/drivers/gpu/drm/amd/display/dc/hubp/dcn50/dcn50_hubp.c @@ -22,7 +22,8 @@ bool hubp50_program_surface_flip_and_addr( struct hubp *hubp, const struct dc_plane_address *address, - bool flip_immediate) + bool flip_immediate, + bool dcc) { struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); @@ -55,8 +56,10 @@ bool hubp50_program_surface_flip_and_addr( if (address->grph.addr.quad_part == 0) break; - REG_UPDATE(DCSURF_SURFACE_CONTROL, - PRIMARY_SURFACE_TMZ, address->tmz_surface); + REG_UPDATE_3(DCSURF_SURFACE_CONTROL, + PRIMARY_SURFACE_TMZ, address->tmz_surface, + PRIMARY_SURFACE_DCC_EN, dcc, + SECONDARY_SURFACE_DCC_EN, dcc); REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0, PRIMARY_SURFACE_ADDRESS_HIGH, @@ -71,9 +74,11 @@ bool hubp50_program_surface_flip_and_addr( || address->video_progressive.chroma_addr.quad_part == 0) break; - REG_UPDATE_2(DCSURF_SURFACE_CONTROL, + REG_UPDATE_4(DCSURF_SURFACE_CONTROL, PRIMARY_SURFACE_TMZ, address->tmz_surface, - PRIMARY_SURFACE_TMZ_C, address->tmz_surface); + PRIMARY_SURFACE_TMZ_C, address->tmz_surface, + PRIMARY_SURFACE_DCC_EN, dcc, + SECONDARY_SURFACE_DCC_EN, dcc); REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C, 0, PRIMARY_SURFACE_ADDRESS_HIGH_C, @@ -96,11 +101,13 @@ bool hubp50_program_surface_flip_and_addr( || address->grph_stereo.right_addr.quad_part == 0) break; - REG_UPDATE_4(DCSURF_SURFACE_CONTROL, + REG_UPDATE_6(DCSURF_SURFACE_CONTROL, PRIMARY_SURFACE_TMZ, address->tmz_surface, PRIMARY_SURFACE_TMZ_C, address->tmz_surface, SECONDARY_SURFACE_TMZ, address->tmz_surface, - SECONDARY_SURFACE_TMZ_C, address->tmz_surface); + SECONDARY_SURFACE_TMZ_C, address->tmz_surface, + PRIMARY_SURFACE_DCC_EN, dcc, + SECONDARY_SURFACE_DCC_EN, dcc); REG_SET(DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C, 0, SECONDARY_SURFACE_ADDRESS_HIGH_C, @@ -139,9 +146,11 @@ bool hubp50_program_surface_flip_and_addr( || address->rgbea.alpha_addr.quad_part == 0) break; - REG_UPDATE_2(DCSURF_SURFACE_CONTROL, + REG_UPDATE_4(DCSURF_SURFACE_CONTROL, PRIMARY_SURFACE_TMZ, address->tmz_surface, - PRIMARY_SURFACE_TMZ_C, address->tmz_surface); + PRIMARY_SURFACE_TMZ_C, address->tmz_surface, + PRIMARY_SURFACE_DCC_EN, dcc, + SECONDARY_SURFACE_DCC_EN, dcc); REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C, 0, PRIMARY_SURFACE_ADDRESS_HIGH_C, @@ -457,7 +466,6 @@ void hubp50_program_surface_config( (void)compat_level; struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); - hubp401_dcc_control(hubp, dcc); hubp50_program_tiling(hubp2, tiling_info, format); hubp401_program_size(hubp, format, plane_size, dcc); hubp2_program_rotation(hubp, rotation, horizontal_mirror); diff --git a/drivers/gpu/drm/amd/display/dc/hubp/dcn50/dcn50_hubp.h b/drivers/gpu/drm/amd/display/dc/hubp/dcn50/dcn50_hubp.h index e7d9bb3623b9..a497a90947b6 100644 --- a/drivers/gpu/drm/amd/display/dc/hubp/dcn50/dcn50_hubp.h +++ b/drivers/gpu/drm/amd/display/dc/hubp/dcn50/dcn50_hubp.h @@ -21,7 +21,8 @@ bool hubp50_program_surface_flip_and_addr( struct hubp *hubp, const struct dc_plane_address *address, - bool flip_immediate); + bool flip_immediate, + bool dcc); void hubp50_program_surface_config( struct hubp *hubp, diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c index 7fa329229ae0..84e146f2509c 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c @@ -2100,7 +2100,8 @@ void dcn10_update_plane_addr(const struct dc *dc, struct pipe_ctx *pipe_ctx) pipe_ctx->plane_res.hubp->funcs->hubp_program_surface_flip_and_addr( pipe_ctx->plane_res.hubp, &address, - flip_immediate); + flip_immediate, + pipe_ctx->plane_state->dcc.enable); } bool dcn10_set_input_transfer_func(struct set_input_transfer_func_params *params) @@ -4184,5 +4185,6 @@ void dcn10_reset_surface_dcc_and_tiling(struct pipe_ctx *pipe_ctx, /* force page flip to see the new content of the framebuffer */ hubp->funcs->hubp_program_surface_flip_and_addr(hubp, &plane_state->address, - true); + true, + plane_state->dcc.enable); } diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c index a3d2385bc731..e5f266b0013d 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c @@ -2818,7 +2818,8 @@ void dcn20_update_plane_addr(const struct dc *dc, struct pipe_ctx *pipe_ctx) pipe_ctx->plane_res.hubp->funcs->hubp_program_surface_flip_and_addr( pipe_ctx->plane_res.hubp, &address, - flip_immediate); + flip_immediate, + pipe_ctx->plane_state->dcc.enable); } void dcn20_unblank_stream(struct pipe_ctx *pipe_ctx, diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c index 916b6804e8e6..c22587188c98 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c @@ -176,7 +176,8 @@ void dcn201_update_plane_addr(const struct dc *dc, struct pipe_ctx *pipe_ctx) pipe_ctx->plane_res.hubp->funcs->hubp_program_surface_flip_and_addr( pipe_ctx->plane_res.hubp, &address, - flip_immediate); + flip_immediate, + pipe_ctx->plane_state->dcc.enable); } /* Blank pixel data during initialization */ diff --git a/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h index 4b2c801421d6..f023bef4fd7e 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h +++ b/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h @@ -95,6 +95,7 @@ struct update_plane_addr_params { struct hubp *hubp; struct dc_plane_address address; bool flip_immediate; + bool dcc; }; struct set_input_transfer_func_params { diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h b/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h index b97f08b20984..a648ed3b012a 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h @@ -176,7 +176,8 @@ struct hubp_funcs { bool (*hubp_program_surface_flip_and_addr)( struct hubp *hubp, const struct dc_plane_address *address, - bool flip_immediate); + bool flip_immediate, + bool dcc); void (*hubp_program_pte_vm)( struct hubp *hubp, -- 2.43.0