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Ip=[165.204.84.17]; Helo=[satlexmb08.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF000015C8.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS7PR12MB9476 X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" From: Tony Cheng [Why] struct dccg has no instance identifier, unlike other DC hardware blocks. Debug and tracing helpers need one to identify the block. [How] Add an inst member to struct dccg and initialize it to 0 in every dccgX_create(), since there is one DCCG instance per ASIC. Reviewed-by: Jun Lei Signed-off-by: Tony Cheng Signed-off-by: Chenyu Chen --- drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.c | 1 + drivers/gpu/drm/amd/display/dc/dccg/dcn201/dcn201_dccg.c | 1 + drivers/gpu/drm/amd/display/dc/dccg/dcn21/dcn21_dccg.c | 1 + drivers/gpu/drm/amd/display/dc/dccg/dcn30/dcn30_dccg.c | 2 ++ drivers/gpu/drm/amd/display/dc/dccg/dcn301/dcn301_dccg.c | 1 + drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c | 1 + drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c | 1 + drivers/gpu/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.c | 1 + drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c | 1 + drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c | 1 + drivers/gpu/drm/amd/display/dc/dccg/dcn42/dcn42_dccg.c | 1 + drivers/gpu/drm/amd/display/dc/dccg/dcn60/dcn60_dccg.c | 1 + drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h | 1 + 13 files changed, 14 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.c b/drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.c index 13ba7f5ce13e..71ebdd54f8f0 100644 --- a/drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.c +++ b/drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.c @@ -212,6 +212,7 @@ struct dccg *dccg2_create( base->ctx = ctx; base->funcs = &dccg2_funcs; + base->inst = 0; dccg_dcn->regs = regs; dccg_dcn->dccg_shift = dccg_shift; dccg_dcn->dccg_mask = dccg_mask; diff --git a/drivers/gpu/drm/amd/display/dc/dccg/dcn201/dcn201_dccg.c b/drivers/gpu/drm/amd/display/dc/dccg/dcn201/dcn201_dccg.c index 5b9ba9a811ea..ee27d7519d2d 100644 --- a/drivers/gpu/drm/amd/display/dc/dccg/dcn201/dcn201_dccg.c +++ b/drivers/gpu/drm/amd/display/dc/dccg/dcn201/dcn201_dccg.c @@ -82,6 +82,7 @@ struct dccg *dccg201_create( base->ctx = ctx; base->funcs = &dccg201_funcs; + base->inst = 0; dccg_dcn->regs = regs; dccg_dcn->dccg_shift = dccg_shift; dccg_dcn->dccg_mask = dccg_mask; diff --git a/drivers/gpu/drm/amd/display/dc/dccg/dcn21/dcn21_dccg.c b/drivers/gpu/drm/amd/display/dc/dccg/dcn21/dcn21_dccg.c index 1f23dfccf07a..d0735022f198 100644 --- a/drivers/gpu/drm/amd/display/dc/dccg/dcn21/dcn21_dccg.c +++ b/drivers/gpu/drm/amd/display/dc/dccg/dcn21/dcn21_dccg.c @@ -158,6 +158,7 @@ struct dccg *dccg21_create( base->ctx = ctx; base->funcs = &dccg21_funcs; + base->inst = 0; dccg_dcn->regs = regs; dccg_dcn->dccg_shift = dccg_shift; dccg_dcn->dccg_mask = dccg_mask; diff --git a/drivers/gpu/drm/amd/display/dc/dccg/dcn30/dcn30_dccg.c b/drivers/gpu/drm/amd/display/dc/dccg/dcn30/dcn30_dccg.c index 9df06df6c7f1..005ca01d7ecc 100644 --- a/drivers/gpu/drm/amd/display/dc/dccg/dcn30/dcn30_dccg.c +++ b/drivers/gpu/drm/amd/display/dc/dccg/dcn30/dcn30_dccg.c @@ -114,6 +114,7 @@ struct dccg *dccg3_create( base->ctx = ctx; base->funcs = &dccg3_funcs; + base->inst = 0; dccg_dcn->regs = regs; dccg_dcn->dccg_shift = dccg_shift; dccg_dcn->dccg_mask = dccg_mask; @@ -139,6 +140,7 @@ struct dccg *dccg30_create( base->ctx = ctx; base->funcs = &dccg3_funcs; + base->inst = 0; dccg_dcn->regs = regs; dccg_dcn->dccg_shift = dccg_shift; dccg_dcn->dccg_mask = dccg_mask; diff --git a/drivers/gpu/drm/amd/display/dc/dccg/dcn301/dcn301_dccg.c b/drivers/gpu/drm/amd/display/dc/dccg/dcn301/dcn301_dccg.c index 837f4e3d1a60..022e8d3dfce2 100644 --- a/drivers/gpu/drm/amd/display/dc/dccg/dcn301/dcn301_dccg.c +++ b/drivers/gpu/drm/amd/display/dc/dccg/dcn301/dcn301_dccg.c @@ -73,6 +73,7 @@ struct dccg *dccg301_create( base->ctx = ctx; base->funcs = &dccg301_funcs; + base->inst = 0; dccg_dcn->regs = regs; dccg_dcn->dccg_shift = dccg_shift; dccg_dcn->dccg_mask = dccg_mask; diff --git a/drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c b/drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c index ce90cba853f7..341509ad6f35 100644 --- a/drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c +++ b/drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c @@ -965,6 +965,7 @@ struct dccg *dccg31_create( base->ctx = ctx; base->funcs = &dccg31_funcs; + base->inst = 0; dccg_dcn->regs = regs; dccg_dcn->dccg_shift = dccg_shift; dccg_dcn->dccg_mask = dccg_mask; diff --git a/drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c b/drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c index 1a4d4cd58ad8..a71851779b37 100644 --- a/drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c +++ b/drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c @@ -429,6 +429,7 @@ struct dccg *dccg314_create( base->ctx = ctx; base->funcs = &dccg314_funcs; + base->inst = 0; dccg_dcn->regs = regs; dccg_dcn->dccg_shift = dccg_shift; dccg_dcn->dccg_mask = dccg_mask; diff --git a/drivers/gpu/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.c b/drivers/gpu/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.c index f75c5aa2d23e..52161c745a48 100644 --- a/drivers/gpu/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.c +++ b/drivers/gpu/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.c @@ -441,6 +441,7 @@ struct dccg *dccg32_create( base->ctx = ctx; base->funcs = &dccg32_funcs; + base->inst = 0; dccg_dcn->regs = regs; dccg_dcn->dccg_shift = dccg_shift; dccg_dcn->dccg_mask = dccg_mask; diff --git a/drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c b/drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c index 4fbd40b518cd..ba624f442915 100644 --- a/drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c +++ b/drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c @@ -2804,6 +2804,7 @@ struct dccg *dccg35_create( base->ctx = ctx; base->funcs = &dccg35_funcs; + base->inst = 0; dccg_dcn->regs = regs; dccg_dcn->dccg_shift = dccg_shift; dccg_dcn->dccg_mask = dccg_mask; diff --git a/drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c b/drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c index 7bff1b9da6f9..a4ece209d600 100644 --- a/drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c +++ b/drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c @@ -999,6 +999,7 @@ struct dccg *dccg401_create( base->ctx = ctx; base->funcs = &dccg401_funcs; + base->inst = 0; dccg_dcn->regs = regs; dccg_dcn->dccg_shift = dccg_shift; dccg_dcn->dccg_mask = dccg_mask; diff --git a/drivers/gpu/drm/amd/display/dc/dccg/dcn42/dcn42_dccg.c b/drivers/gpu/drm/amd/display/dc/dccg/dcn42/dcn42_dccg.c index c9ea3b166876..cf6fffc2b26e 100644 --- a/drivers/gpu/drm/amd/display/dc/dccg/dcn42/dcn42_dccg.c +++ b/drivers/gpu/drm/amd/display/dc/dccg/dcn42/dcn42_dccg.c @@ -382,6 +382,7 @@ struct dccg *dccg42_create( base->ctx = ctx; base->funcs = &dccg42_funcs; + base->inst = 0; dccg_dcn->regs = regs; dccg_dcn->dccg_shift = dccg_shift; dccg_dcn->dccg_mask = dccg_mask; diff --git a/drivers/gpu/drm/amd/display/dc/dccg/dcn60/dcn60_dccg.c b/drivers/gpu/drm/amd/display/dc/dccg/dcn60/dcn60_dccg.c index 8e2f88913e4c..eb8b7e12d2f1 100644 --- a/drivers/gpu/drm/amd/display/dc/dccg/dcn60/dcn60_dccg.c +++ b/drivers/gpu/drm/amd/display/dc/dccg/dcn60/dcn60_dccg.c @@ -179,6 +179,7 @@ struct dccg *dccg60_create( base->ctx = ctx; base->funcs = &dccg60_funcs; + base->inst = 0; dccg_dcn->regs = regs; dccg_dcn->dccg_shift = dccg_shift; dccg_dcn->dccg_mask = dccg_mask; diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h b/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h index e756719308ab..4b7c55eeb0c6 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h @@ -193,6 +193,7 @@ struct dcn_dccg_reg_state { struct dccg { struct dc_context *ctx; const struct dccg_funcs *funcs; + int inst; int pipe_dppclk_khz[MAX_PIPES]; int ref_dppclk; bool dpp_clock_gated[MAX_PIPES]; -- 2.43.0