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Ip=[165.204.84.17]; Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN7PEPF0000009E.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY8PR12MB8297 X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" [Why] Commit c3fb1fb9e65f ("drm/amd/display: Fix warnings") aligned the signedness of a large number of DC values, but two hunks of the original change were not carried over: - struct frl_cap_chk_params_fixed31_32 still declares audio_packet_type, h_active and h_blank as int. All three only ever hold non-negative values: h_active and h_blank are HDMI timing quantities counted in pixels, and audio_packet_type is only compared against the positive HDMI audio packet type constants 0x02, 0x07, 0x08, 0x09 and 0x0e in frl_capacity_computations_common(). - hpo_enc3_read_state() still declares pixel_encoding, color_depth and odm_combine as int and passes their addresses to REG_GET_2()/REG_GET(), whose generic_reg_get*() backends take uint32_t *. The mismatch is only hidden by the explicit (uint32_t *) cast inside the REG_GET macros. The DCN401 equivalent, hpo_enc401_read_state(), already uses uint32_t. [How] Widen the three struct fields to unsigned int/uint32_t and the three locals to uint32_t so the types match how the values are produced and consumed. No computed value changes. Reviewed-by: Alex Hung Signed-off-by: Chenyu Chen --- drivers/gpu/drm/amd/display/dc/dc.h | 6 +++--- .../amd/display/dc/hpo/dcn30/dcn30_hpo_frl_stream_encoder.c | 6 +++--- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 634c0b7686bb..b6c71ebb7ea7 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -112,10 +112,10 @@ struct frl_cap_chk_params_fixed31_32 { int lanes; struct fixed31_32 f_pixel_clock_nominal; /* Pixel Clock rate (Hz) */ struct fixed31_32 r_bit_nominal; /* FRL bitrate (bps) */ - int audio_packet_type; + unsigned int audio_packet_type; struct fixed31_32 f_audio; /* Audio rate (Hz) */ - int h_active; /* Active pixels per line */ - int h_blank; /* Blanking pixels per line */ + uint32_t h_active; /* Active pixels per line */ + uint32_t h_blank; /* Blanking pixels per line */ int bpc; /* Bits per component */ int vic; /* Video Identification Code */ diff --git a/drivers/gpu/drm/amd/display/dc/hpo/dcn30/dcn30_hpo_frl_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/hpo/dcn30/dcn30_hpo_frl_stream_encoder.c index cff5c95a771c..f4c21998d845 100644 --- a/drivers/gpu/drm/amd/display/dc/hpo/dcn30/dcn30_hpo_frl_stream_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/hpo/dcn30/dcn30_hpo_frl_stream_encoder.c @@ -921,9 +921,9 @@ void hpo_enc3_read_state( struct hpo_frl_stream_encoder *enc, struct hpo_frl_stream_encoder_state *state) { - int pixel_encoding; - int color_depth; - int odm_combine; + uint32_t pixel_encoding; + uint32_t color_depth; + uint32_t odm_combine; struct dcn30_hpo_frl_stream_encoder *enc3 = DCN30_HPO_FRL_STRENC_FROM_HPO_FRL_STRENC(enc); ASSERT(state); -- 2.43.0