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Ip=[165.204.84.17]; Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN7PEPF00000096.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN0PR12MB5762 X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" This commit implements device PMC handler Signed-off-by: Zhu Lingshan --- drivers/gpu/drm/amd/amdgpu/amdgpu_profiler.c | 6 +- drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c | 68 ++++++++++++++++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_userq.h | 2 + 3 files changed, 75 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_profiler.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_profiler.c index 254fb8d77d80..f40c848331a0 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_profiler.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_profiler.c @@ -95,7 +95,11 @@ int amdgpu_profiler_set_perfcount(struct amdgpu_device *adev, mutex_unlock(&adev->pmc_profiler.lock); - return ret; + if (ret) + return ret; + + /* no racings because the device was reserved by pmc_profiler.owner */ + return amdgpu_set_perfcount(adev, enable); } static int amdgpu_profiler_check_access(struct drm_device *dev) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c index 45e4225c0201..8a1f0841e8e7 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c @@ -1541,6 +1541,74 @@ int amdgpu_userq_resume(struct amdgpu_device *adev) return 0; } +static void amdgpu_userq_set_perfcount(struct amdgpu_usermode_queue *queue, + bool enable) +{ + struct amdgpu_userq_mgr *uq_mgr = queue->userq_mgr; + struct amdgpu_device *adev = uq_mgr->adev; + struct amdgpu_mqd *mqd_funcs = &adev->mqds[queue->queue_type]; + int r; + + /* IP does not support PMC */ + if (!mqd_funcs->set_mqd_perfcount) + return; + + mutex_lock(&uq_mgr->userq_mutex); + queue->userq_prop->perfcount_enable = enable; + + if (queue->state == AMDGPU_USERQ_STATE_MAPPED) { + r = amdgpu_userq_unmap_helper(queue); + if (r) { + drm_file_err(uq_mgr->file, + "Failed to unmap user queue %llu when updating PMC\n", + queue->doorbell_index); + } else { + mqd_funcs->set_mqd_perfcount(queue->mqd.cpu_ptr, + queue->userq_prop); + r = amdgpu_userq_map_helper(queue); + if (r) + drm_file_err(uq_mgr->file, + "Failed to map user queue %llu when updating PMC\n", + queue->doorbell_index); + } + } else { + drm_dbg_driver(adev_to_drm(adev), + "user queue %llu is in state %d, skip it when updating PMC\n", + queue->doorbell_index, queue->state); + } + + mutex_unlock(&uq_mgr->userq_mutex); +} + +/* set perfcount for every queue on the device. */ +int amdgpu_set_perfcount(struct amdgpu_device *adev, bool enable) +{ + struct amdgpu_usermode_queue *queue; + unsigned long queue_id = 0; + + if (amdgpu_in_reset(adev)) + return -EIO; + + if (adev->userq_halt_for_enforce_isolation) + return -EAGAIN; + + queue = amdgpu_userq_xa_find(&adev->userq_doorbell_xa, &queue_id); + while (queue) { + amdgpu_userq_set_perfcount(queue, enable); + amdgpu_userq_put(queue); + + if (queue_id == ULONG_MAX) + break; + + /* find next queue */ + queue_id++; + queue = amdgpu_userq_xa_find(&adev->userq_doorbell_xa, + &queue_id); + } + + return 0; +} + int amdgpu_userq_stop_sched_for_enforce_isolation(struct amdgpu_device *adev, u32 idx) { diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.h index 4c9a71b56792..2fcde5955d4d 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.h @@ -189,6 +189,8 @@ int amdgpu_userq_stop_sched_for_enforce_isolation(struct amdgpu_device *adev, u32 idx); int amdgpu_userq_start_sched_for_enforce_isolation(struct amdgpu_device *adev, u32 idx); + +int amdgpu_set_perfcount(struct amdgpu_device *adev, bool enable); void amdgpu_userq_reset_work(struct work_struct *work); void amdgpu_userq_pre_reset(struct amdgpu_device *adev); int amdgpu_userq_post_reset(struct amdgpu_device *adev, bool vram_lost); -- 2.55.0