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Ip=[165.204.84.17]; Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN7PEPF00000090.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH4PR12MB720178 X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" This commit implements a new callback set_mqd_perfcount in struct amdgpu_mqd. This callback helps setting mqd->compute_perfcount_enable from amdgpu_mqd_prop->perfcount_enable. This is a per-IP callback and it is NULL if an IP does not support PMC. This commit also implements set_mqd_perfcount for GFX11. Signed-off-by: Zhu Lingshan --- drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h | 6 ++++++ drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 11 +++++++++++ 2 files changed, 17 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h index 7a5499ec1171..f7ae3d5484da 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h @@ -479,12 +479,18 @@ struct amdgpu_mqd_prop { uint64_t ctx_save_area_addr; uint32_t ctx_save_area_size; uint32_t ctl_stack_size; + /* PMC compute_perfcount_enable that programmed into this queue's MQD */ + bool perfcount_enable; }; struct amdgpu_mqd { unsigned mqd_size; int (*init_mqd)(struct amdgpu_device *adev, void *mqd, struct amdgpu_mqd_prop *p); + /* Per-IP callback to set compute_perfcount_enable, + * NULL when this IP's MQD has no perfcount_enable field. + */ + void (*set_mqd_perfcount)(void *mqd, struct amdgpu_mqd_prop *p); }; /* diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c index 254a72f26ec5..252a1096b4a0 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c @@ -4323,6 +4323,7 @@ static int gfx_v11_0_compute_mqd_init(struct amdgpu_device *adev, void *m, mqd->header = 0xC0310800; mqd->compute_pipelinestat_enable = 0x00000001; + mqd->compute_perfcount_enable = prop->perfcount_enable; mqd->compute_static_thread_mgmt_se0 = 0xffffffff; mqd->compute_static_thread_mgmt_se1 = 0xffffffff; mqd->compute_static_thread_mgmt_se2 = 0xffffffff; @@ -4459,6 +4460,14 @@ static int gfx_v11_0_compute_mqd_init(struct amdgpu_device *adev, void *m, return 0; } +static void gfx_v11_0_compute_mqd_set_perfcount(void *m, + struct amdgpu_mqd_prop *prop) +{ + struct v11_compute_mqd *mqd = m; + + mqd->compute_perfcount_enable = prop->perfcount_enable; +} + static int gfx_v11_0_kiq_init_register(struct amdgpu_ring *ring) { struct amdgpu_device *adev = ring->adev; @@ -7263,6 +7272,8 @@ static void gfx_v11_0_set_mqd_funcs(struct amdgpu_device *adev) sizeof(struct v11_compute_mqd); adev->mqds[AMDGPU_HW_IP_COMPUTE].init_mqd = gfx_v11_0_compute_mqd_init; + adev->mqds[AMDGPU_HW_IP_COMPUTE].set_mqd_perfcount = + gfx_v11_0_compute_mqd_set_perfcount; } static void gfx_v11_0_set_user_wgp_inactive_bitmap_per_sh(struct amdgpu_device *adev, -- 2.55.0