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Thu, 24 Sep 2026 01:35:38 -0500 From: Victor Zhao To: , , , CC: , , Victor Zhao Subject: [PATCH v2 2/2] drm/amdgpu: Read RLC GPU clock on GFX12.1 VF Date: Thu, 24 Sep 2026 14:35:18 +0800 Message-ID: <20260924063519.688340-2-Victor.Zhao@amd.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20260924063519.688340-1-Victor.Zhao@amd.com> References: <20260924063519.688340-1-Victor.Zhao@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH1PEPF0000A34C:EE_|PH7PR12MB6465:EE_ X-MS-Office365-Filtering-Correlation-Id: 68b7adfb-8fc1-47ca-ede1-08df1a060daf X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|36860700016|1800799024|82310400026|376014|23010399003|22082099003|18002099003|56012099006|11063799006|10067099003; X-Microsoft-Antispam-Message-Info: 1c/xZXcY6AMmR4W7PHDVaEjupaRxosFxxx2XKCIeaWxTqAIAyGkH4L/ZW8eJPXoWOMoELhZaSTJoFmmfO9zujR1SxsK0QwwmYdGwhnq/xQe5UMA7iVLKoO07AarHGTjozrJgtPRJogwCk+gtoJ8ZNe4D3JLIxgoTfr39vvUC5lJTkt39oa2pqEEx7v/OdXD3ZczAEr2STz/qaXba2pRX/+C918Ha01wKess4/FAsENPc2PTtIObOJ4dTyKz0ycdIG0A89Ry27El/2JpxFsr/FmeloNz5EwDONaWzBumDO51dg/P+owIjWNIE8Xpr789pu58WlUZpeVd1ZF+H0dKZfLLFm+7Iu67OXF64mSHZGlUmJpKVrliQsZIHJqxzu6PQoHNMrblp7MeO8t7SZxsCinJhD4TVKlKbjtD5Lau+rWO7lW2vmTR4r2f0Q7TGqQkEm8oi2GNVMZyvD37qG2Cc94f1/ceoIA14/ACXkKDdHz27LVHZ6Zb4dMDCJpr4Hwd6v1PVHagEbVVkg2KHao6vXP+uI5OO9ggVWUVSZPJoDqHkMKLNoeuzYoBNEdIPq+njoiAbPQRWlu+fKm5P1YK/m2E9tD9V9ohMgENSpLEz0iNlhcHykKbGbXvsyhQB9/l4ySCXsB/ylpok5VIQCTYx0nuPQd2ZAAlgEA8BSavalJlOidhG5/HyGIJy7OGcWVeL X-Forefront-Antispam-Report: CIP:165.204.84.17; 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Ip=[165.204.84.17]; Helo=[satlexmb08.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH1PEPF0000A34C.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB6465 X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" [why] VF timestamp queries need a TSC sample independent of CP/MES. The SMUIO path is not safe on VF. [how] Capture via RLC_CAPTURE_GPU_CLOCK_COUNT and read the consecutive count registers with amdgpu_mes_rreg64(). Signed-off-by: Victor Zhao --- drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c b/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c index d6f70d33201a0..3c8133c94d6fc 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c @@ -3168,10 +3168,36 @@ static int gfx_v12_1_wait_for_idle(struct amdgpu_ip_block *ip_block) return -ETIMEDOUT; } +static uint64_t gfx_v12_1_get_rlc_gpu_clock_counter(struct amdgpu_device *adev) +{ + uint64_t clock = 0; + uint32_t reg; + + if (!down_read_trylock(&adev->reset_domain->sem)) + return 0; + if (amdgpu_device_skip_hw_access(adev) || + !adev->mes.ring[0].sched.ready) + goto unlock_reset; + + mutex_lock(&adev->gfx.gpu_clock_mutex); + WREG32_SOC15(GC, GET_INST(GC, 0), regRLC_CAPTURE_GPU_CLOCK_COUNT, 1); + reg = SOC15_REG_OFFSET(GC, GET_INST(GC, 0), + regRLC_GPU_CLOCK_COUNT_LSB); + clock = amdgpu_mes_rreg64(adev, reg, 0); + mutex_unlock(&adev->gfx.gpu_clock_mutex); + +unlock_reset: + up_read(&adev->reset_domain->sem); + return clock; +} + static uint64_t gfx_v12_1_get_gpu_clock_counter(struct amdgpu_device *adev) { uint64_t clock = 0; + if (amdgpu_sriov_vf(adev)) + return gfx_v12_1_get_rlc_gpu_clock_counter(adev); + if (adev->smuio.funcs && adev->smuio.funcs->get_gpu_clock_counter) clock = adev->smuio.funcs->get_gpu_clock_counter(adev); -- 2.50.1