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Ip=[165.204.84.17]; Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN7PEPF000000A4.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH8PR12MB8432 X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" Only the mode that halts runtime services flags the device once the bad page threshold is reached, so on a default or warn-only threshold the in-band CPER record and the out-of-band RMA reason are not emitted even though the table records that the threshold was hit. Track the threshold condition separately from the halt decision and use it to drive the report, so every mode except the debug one tells the host that the device reached its bad page budget. Signed-off-by: Xiang Liu --- drivers/gpu/drm/amd/ras/core/ras.h | 1 + drivers/gpu/drm/amd/ras/core/ras_eeprom_mgr.c | 4 ++++ drivers/gpu/drm/amd/ras/core/ras_umc.c | 2 +- 3 files changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/ras/core/ras.h b/drivers/gpu/drm/amd/ras/core/ras.h index fcea457d5cbe..8c6e8ab89c58 100644 --- a/drivers/gpu/drm/amd/ras/core/ras.h +++ b/drivers/gpu/drm/amd/ras/core/ras.h @@ -415,6 +415,7 @@ struct ras_core_context { bool poison_supported; bool is_rma; + bool bad_page_over_threshold; bool is_initialized; bool in_early_init; bool early_init_service_enabled; diff --git a/drivers/gpu/drm/amd/ras/core/ras_eeprom_mgr.c b/drivers/gpu/drm/amd/ras/core/ras_eeprom_mgr.c index 1781d037ef13..2f33e3132f76 100644 --- a/drivers/gpu/drm/amd/ras/core/ras_eeprom_mgr.c +++ b/drivers/gpu/drm/amd/ras/core/ras_eeprom_mgr.c @@ -294,6 +294,9 @@ int ras_eeprom_mgr_check_and_report_status(struct ras_core_context *ras_core, bo RAS_DEV_ERR(ras_core->dev, "RAS records:%d exceed threshold:%d", valid_err_count, mgr->ras_err_threshold); + if (mgr->work_mode_over_thresh != RAS_WORK_MODE_OVER_THRESH_DEBUG) + ras_core->bad_page_over_threshold = true; + if (mgr->work_mode_over_thresh == RAS_WORK_MODE_OVER_THRESH_STRICT) { RAS_DEV_WARN(ras_core->dev, "Please consult AMD Service Action Guide (SAG) for appropriate service procedures\n"); @@ -315,6 +318,7 @@ int ras_eeprom_mgr_check_and_report_status(struct ras_core_context *ras_core, bo RAS_DEV_ERR(ras_core->dev, "Failed to resize RAS table\n"); } else { ras_core->is_rma = false; + ras_core->bad_page_over_threshold = false; RAS_DEV_INFO(ras_core->dev, "records:%d threshold:%d, resetting RAS table header signature", valid_err_count, mgr->ras_err_threshold); diff --git a/drivers/gpu/drm/amd/ras/core/ras_umc.c b/drivers/gpu/drm/amd/ras/core/ras_umc.c index c2663f84a883..6af41c68d83b 100644 --- a/drivers/gpu/drm/amd/ras/core/ras_umc.c +++ b/drivers/gpu/drm/amd/ras/core/ras_umc.c @@ -701,7 +701,7 @@ void ras_umc_report_badpage_info(struct ras_core_context *ras_core) &ras_umc->last_channel_bitmap); } - if (ras_core->is_rma) + if (ras_core->is_rma || ras_core->bad_page_over_threshold) ras_core_event_notify(ras_core, RAS_EVENT_ID__DEVICE_RMA, NULL); } -- 2.34.1