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Tue, 10 Nov 2026 19:41:01 -0600 From: Wayne Lin To: CC: Harry Wentland , Leo Li , Aurabindo Pillai , Roman Li , Wayne Lin , Tom Chung , "Fangzhi Zuo" , Dan Wheeler , Ray Wu , Ivan Lipski , Alex Hung , James Lin , Chenyu Chen , Dillon Varone Subject: [PATCH 11/74] drm/amd/display: Relax stutter constraints for DRR streams Date: Wed, 11 Nov 2026 09:28:17 +0800 Message-ID: <20261111014100.3596072-12-Wayne.Lin@amd.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20261111014100.3596072-1-Wayne.Lin@amd.com> References: <20261111014100.3596072-1-Wayne.Lin@amd.com> X-Archived-By: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN2PEPF0000A805:EE_|DS0PR12MB6463:EE_ X-MS-Office365-Filtering-Correlation-Id: 9cf68668-279d-4872-a566-08df3f94da07 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|36860700016|1800799024|376014|82310400026|23010399003|261102123227099003|56012099006|11063799006|261021123027099003|261021121427099003|261009223027099003|261022075727099003|261026140227099003|261022105027099003|261026121527099003|261028144727099003|10067099003|22082099003|18002099003|3023799007; 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How: Add a PMO option to relax the blanking factor for fixed-DRR streams, and apply the relaxed threshold when checking Z8 and regular stutter latency requirements. Signed-off-by: Dillon Varone Signed-off-by: Wayne Lin --- .../dc/dml2_0/dml21/inc/dml_top_types.h | 1 + .../dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c | 19 ++++++++++++++++--- 2 files changed, 17 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/dml_top_types.h b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/dml_top_types.h index 75a24a85775e..fd7ccefc7fb7 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/dml_top_types.h +++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/dml_top_types.h @@ -83,6 +83,7 @@ struct dml2_pmo_options { bool force_optional_uclk_pstate_support; bool force_optional_mcache_support; bool force_optional_ppt_temp_read_admissibility; + bool relax_stutter_constraint_for_drr; struct dml2_pmo_pstate_strategy *override_strategy_lists[DML2_MAX_PLANES]; unsigned int num_override_strategies_per_list[DML2_MAX_PLANES]; }; diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c index de078ccd91a2..3584dbe4c9fb 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c +++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c @@ -8,7 +8,7 @@ #include "dml2_pmo_dcn4_fams2.h" static const double MIN_VACTIVE_MARGIN_PCT = 0.25; // We need more than non-zero margin because DET buffer granularity can alter vactive latency hiding -static const double MIN_BLANK_STUTTER_FACTOR = 3.0; +static const double MIN_BLANK_STUTTER_FACTOR = 3.0f; static const struct dml2_pmo_pstate_strategy base_strategy_list_1_display[] = { // VActive Preferred @@ -2357,6 +2357,16 @@ bool pmo_dcn4_fams2_optimize_for_pstate_support(struct dml2_pmo_optimize_for_pst return success; } +static bool should_relax_stutter_constraint_for_stream(const struct dml2_pmo_init_for_stutter_in_out *in_out, + unsigned int stream_index) +{ + // relax the stutter constraint when: + // 1. Stream has DRR fixed enabled (assumed blank is extended sufficiently beyond nominal) + // 2. The option to relax stutter constraint is enabled in PMO options. + return in_out->base_display_config->display_config.stream_descriptors[stream_index].timing.drr_config.drr_active_fixed && + in_out->instance->options->relax_stutter_constraint_for_drr; +} + bool pmo_dcn4_fams2_init_for_stutter(struct dml2_pmo_init_for_stutter_in_out *in_out) { bool success = true; @@ -2365,6 +2375,7 @@ bool pmo_dcn4_fams2_init_for_stutter(struct dml2_pmo_init_for_stutter_in_out *in bool z8_stutter_optimization_too_expensive = false; bool stutter_optimization_too_expensive = false; double line_time_us, vblank_nom_time_us; + double stutter_factor; unsigned int i; @@ -2382,15 +2393,17 @@ bool pmo_dcn4_fams2_init_for_stutter(struct dml2_pmo_init_for_stutter_in_out *in } for (i = 0; i < in_out->base_display_config->display_config.num_streams; i++) { + stutter_factor = should_relax_stutter_constraint_for_stream(in_out, i) ? 1.0f : MIN_BLANK_STUTTER_FACTOR; + line_time_us = (double)in_out->base_display_config->display_config.stream_descriptors[i].timing.h_total / (in_out->base_display_config->display_config.stream_descriptors[i].timing.pixel_clock_khz * 1000) * 1000000; vblank_nom_time_us = line_time_us * in_out->base_display_config->display_config.stream_descriptors[i].timing.vblank_nom; - if (vblank_nom_time_us < pmo->soc_bb->power_management_parameters.z8_stutter_exit_latency_us * MIN_BLANK_STUTTER_FACTOR) { + if (vblank_nom_time_us < pmo->soc_bb->power_management_parameters.z8_stutter_exit_latency_us * stutter_factor) { z8_stutter_optimization_too_expensive = true; break; } - if (vblank_nom_time_us < pmo->soc_bb->power_management_parameters.stutter_enter_plus_exit_latency_us * MIN_BLANK_STUTTER_FACTOR) { + if (vblank_nom_time_us < pmo->soc_bb->power_management_parameters.stutter_enter_plus_exit_latency_us * stutter_factor) { stutter_optimization_too_expensive = true; break; } -- 2.43.0