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Tue, 10 Nov 2026 19:41:51 -0600 From: Wayne Lin To: CC: Harry Wentland , Leo Li , Aurabindo Pillai , Roman Li , Wayne Lin , Tom Chung , "Fangzhi Zuo" , Dan Wheeler , Ray Wu , Ivan Lipski , Alex Hung , James Lin , Chenyu Chen Subject: [PATCH 24/74] drm/amd/display: Enable SST PCON FRL DSC passthrough Date: Wed, 11 Nov 2026 09:28:30 +0800 Message-ID: <20261111014100.3596072-25-Wayne.Lin@amd.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20261111014100.3596072-1-Wayne.Lin@amd.com> References: <20261111014100.3596072-1-Wayne.Lin@amd.com> X-Archived-By: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF0000231A:EE_|SA3PR12MB8045:EE_ X-MS-Office365-Filtering-Correlation-Id: 6937eb74-6de5-4567-1887-08df3f94f7a7 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|376014|23010399003|1800799024|36860700016|82310400026|261009223027099003|56012099006|11063799006|261021123027099003|261026121527099003|261021121427099003|261102123227099003|22082099003|18002099003|10067099003; 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DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: A2JK89O691DBMXnCYswMOl2s7zOJXVKgDvF8N1mBZ6Uobp5E732ncUyw5g8YTe9N3a1TUacoTLR+jlPGoYZeqQ//GPbFuj06kZ6kIw64VwBfXmoYF9f1yO3m/JoWeNPpGPqsybqplU6gSk8QKev8gjHV3/Pn/ePDYuiRZ+gUfjk6dNeO9ozmLYdpobWkAVBNFVm0iY/3iRkVVoVDgndrF+tZy+YFi94CX8+UwLM6e8y2dQx2LcLluMPY0F60nCOAoM5AcLStSNF71Yjjjt/lyzpqCh+/O9cq7tVS9Bssta42GEcjVcHchIdRiEkWxqLjioNkimHWnwc7/n0qMdhUfud7e9kytybtCrp41EQGT7p8sfPAh5KZd6gFj12jLaALs3phMB6x2MUWtBkWwQaC2y/h2FOA61agNKrT30iDVZ9wKBI7T73Dmjj+iB4p2obQ X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Nov 2026 01:41:55.1512 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 6937eb74-6de5-4567-1887-08df3f94f7a7 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF0000231A.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA3PR12MB8045 X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "amd-gfx" X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=4.0.1 X-Spam-Checker-Version: SpamAssassin 4.0.1 (2024-03-26) on aws-us-west-2-korg-listserv-alma10-1 From: Fangzhi Zuo [Why] The SST DSC passthrough to FRL endpoint is not activated yet, that leads to an FRL sink received DSC_DECODING instead of DSC_PASSTHROUGH even when the stream selected FRL DSC. [How] Make the SST PCON path unconditional and select DSC_PASSTHROUGH when DSC is enabled for an FRL stream. Preserve the existing default DSC_DECODING and DSC_DISABLE values for non-FRL enable and disable operations. Cc: Ivan Lipski Signed-off-by: Fangzhi Zuo Signed-off-by: Wayne Lin --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c index 3067ac5bb0cd..6192c0f6086d 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c @@ -1022,10 +1022,15 @@ bool dm_helpers_dp_write_dsc_enable( "SST_DSC Send DSC %s to SST RX\n", enable_dsc ? "enable" : "disable"); } else if (stream->sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER) { + if (enable && stream->timing.dsc_cfg.is_frl) + enable_dsc = DSC_PASSTHROUGH; + ret = dm_helpers_dp_write_dpcd(ctx, stream->link, DP_DSC_ENABLE, &enable_dsc, 1); drm_dbg_dp(dev, - "SST_DSC Send DSC %s to DP-HDMI PCON\n", - enable_dsc ? "enable" : "disable"); + "SST_DSC Send DSC %s to %s\n", + enable_dsc ? "enable" : "disable", + stream->timing.dsc_cfg.is_frl ? "HDMI FRL RX" : + "DP-HDMI PCON"); } } -- 2.43.0