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Ip=[165.204.84.17]; Helo=[satlexmb08.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN2PEPF0000A803.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ2PR12MB8652 X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "amd-gfx" X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=4.0.1 X-Spam-Checker-Version: SpamAssassin 4.0.1 (2024-03-26) on aws-us-west-2-korg-listserv-alma10-1 From: Ashwin Santhosh why: For some visual confirm modes DMCUB programs the MPCC background color and the driver leaves the pipe color all zero to signal that. The driver still programmed that placeholder on every plane update, which stomped the color firmware had written. Firmware only repaints across a modeset, so with visual confirm set to FAMS2 the bar went black after resizing a window and stayed black until the next mode change. The same stomp applies to the PSR, FAMS, and REPLAY, which also leave the color to firmware. how: Add should_driver_program_visual_confirm, which returns false when visual confirm is disabled or set to a mode whose color firmware owns. For FAMS2 the driver still paints all pipes grey while FAMS2 is not in use, so that case checks dc_state_is_fams2_in_use rather than blocking the mode outright. Call the helper from dcn10_update_visual_confirm_color, which covers every caller of the hwss hook, and from hwss_build_fast_sequence, which programs the color directly and is the only path that bypasses the hook. Cc: Alvin Lee Signed-off-by: Ashwin Santhosh Signed-off-by: Wayne Lin --- .../drm/amd/display/dc/core/dc_hw_sequencer.c | 24 ++++++++++++++++++- .../amd/display/dc/hwss/dcn10/dcn10_hwseq.c | 3 +++ .../drm/amd/display/dc/hwss/hw_sequencer.h | 7 ++++++ 3 files changed, 33 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c index 2384cbf16ee1..32a33d29835e 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c @@ -806,6 +806,28 @@ void get_fams2_visual_confirm_color( } } +bool should_driver_program_visual_confirm(const struct dc *dc, const struct dc_state *context) +{ + switch (dc->debug.visual_confirm) { + case VISUAL_CONFIRM_DISABLE: + return false; + /* DMCUB owns the color for these modes. Programming ours stomps what FW + * wrote, and FW only repaints across a modeset, so the bar stays stale. + */ + case VISUAL_CONFIRM_PSR: + case VISUAL_CONFIRM_FAMS: + case VISUAL_CONFIRM_REPLAY: + return false; + case VISUAL_CONFIRM_FAMS2: + /* FW owns the color only while FAMS2 runs. When it is not in use the + * driver paints all pipes grey, and FW does not cover that case. + */ + return !dc_state_is_fams2_in_use(dc, context); + default: + return true; + } +} + static bool get_update_dchubp_dpp_flags_status(struct pipe_ctx *pipe) { if (!pipe->plane_state) { @@ -1644,7 +1666,7 @@ void hwss_build_fast_sequence(struct dc *dc, block_sequence[*num_steps].func = DPP_SET_OUTPUT_TRANSFER_FUNC; (*num_steps)++; } - if (dc->debug.visual_confirm != VISUAL_CONFIRM_DISABLE && + if (should_driver_program_visual_confirm(dc, context) && dc->hwss.update_visual_confirm_color) { block_sequence[*num_steps].params.update_visual_confirm_params.mpc = dc->res_pool->mpc; block_sequence[*num_steps].params.update_visual_confirm_params.color = ¤t_mpc_pipe->visual_confirm_color; diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c index 46a134301526..79c0f55d11e8 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c @@ -2951,6 +2951,9 @@ void dcn10_update_visual_confirm_color(struct dc *dc, { struct mpc *mpc = dc->res_pool->mpc; + if (!should_driver_program_visual_confirm(dc, dc->current_state)) + return; + if (mpc->funcs->set_bg_color) { mpc->funcs->set_bg_color(mpc, &(pipe_ctx->visual_confirm_color), mpcc_id); } diff --git a/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h index d02834639ab3..a6c743d0cc58 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h +++ b/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h @@ -2157,6 +2157,13 @@ void get_fams2_visual_confirm_color( struct pipe_ctx *pipe_ctx, struct tg_color *color); +/* False for modes whose confirm color DMCUB programs, so the driver leaves + * MPCC_BG alone instead of stomping it. Pass the state being programmed. + */ +bool should_driver_program_visual_confirm( + const struct dc *dc, + const struct dc_state *context); + void get_mclk_switch_visual_confirm_color( struct pipe_ctx *pipe_ctx, struct tg_color *color); -- 2.43.0