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Ip=[165.204.84.17]; Helo=[satlexmb08.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN2PEPF0000A801.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH1PR12MB9671 X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "amd-gfx" X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=4.0.1 X-Spam-Checker-Version: SpamAssassin 4.0.1 (2024-03-26) on aws-us-west-2-korg-listserv-alma10-1 From: Tony Cheng [Why] DC2 read the VBIOS accelerated-mode bit with a direct BIOS call. The core layer must not access hardware. [How] Add a query builder that emits one accelerated-mode read into an output target. The core layer builds and executes it in place before it accepts a commit or an update. Cc: Jun Lei Signed-off-by: Tony Cheng Signed-off-by: Wayne Lin --- .../amd/display/dc/bls_builder/bls_builder.h | 2 + .../dc/bls_builder/dcn401_init_builder.c | 32 +++++++++++ .../gpu/drm/amd/display/dc/core2/dc_core2.c | 53 +++++++++++++------ 3 files changed, 72 insertions(+), 15 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/bls_builder/bls_builder.h b/drivers/gpu/drm/amd/display/dc/bls_builder/bls_builder.h index 954adc590ed4..9a3907bf950a 100644 --- a/drivers/gpu/drm/amd/display/dc/bls_builder/bls_builder.h +++ b/drivers/gpu/drm/amd/display/dc/bls_builder/bls_builder.h @@ -26,6 +26,7 @@ enum bls_builder_name { DCN_DECL_INITIALIZATION_LEGACY, DCN_DECL_NON_SEAMLESS_COMMIT, DCN_DECL_SEAMLESS_UPDATE, + DCN_DECL_QUERY_ACCELERATED_MODE, BLS_BUILDER_NAME_COUNT, }; @@ -51,6 +52,7 @@ struct bls_builder_output_targets { union { struct bls_builder_output_init *DCN_DECL_INITIALIZATION; struct bls_builder_legacy_hw_init_info *DCN_DECL_INITIALIZATION_LEGACY; + bool *DCN_DECL_QUERY_ACCELERATED_MODE; }; }; diff --git a/drivers/gpu/drm/amd/display/dc/bls_builder/dcn401_init_builder.c b/drivers/gpu/drm/amd/display/dc/bls_builder/dcn401_init_builder.c index 75fd4be3690a..1dc502c0839c 100644 --- a/drivers/gpu/drm/amd/display/dc/bls_builder/dcn401_init_builder.c +++ b/drivers/gpu/drm/amd/display/dc/bls_builder/dcn401_init_builder.c @@ -386,6 +386,31 @@ static enum bls_builder_result dcn401_build_initialization( return BLS_BUILD_ERROR_UNSUPPORTED_STATE_UPDATE; } +/* Reads the VBIOS accelerated-mode bit into the caller's out-target. */ +static enum bls_builder_result dcn401_build_accelerated_mode_query( + struct bls_builder_declarative_params *params) +{ + union block_sequence_params bls_params = {0}; + struct block_sequence_state sequence; + struct dc_bios *dcb; + + if (!params || !params->dc || !params->dc->ctx || !params->out_targets || + !params->out_targets->DCN_DECL_QUERY_ACCELERATED_MODE) + return BLS_BUILD_ERROR_RESOURCE_MAPPING; + dcb = params->dc->ctx->dc_bios; + if (!dcb || !dcb->funcs || !dcb->funcs->is_accelerated_mode) + return BLS_BUILD_ERROR_RESOURCE_MAPPING; + + sequence.steps = params->head_sequence; + sequence.num_steps = ¶ms->head_num_steps; + bls_params.bios_is_accelerated_mode_params.dcb = dcb; + bls_params.bios_is_accelerated_mode_params.out_accelerated_mode = + params->out_targets->DCN_DECL_QUERY_ACCELERATED_MODE; + if (!bls_append(&sequence, BIOS_IS_ACCELERATED_MODE, &bls_params)) + return BLS_BUILD_ERROR_RESOURCE_MAPPING; + return BLS_BUILD_SUCCESS; +} + const struct bls_builder *dcn401_bls_builder_create( enum bls_builder_name name) { @@ -401,6 +426,11 @@ const struct bls_builder *dcn401_bls_builder_create( .check_capability = dcn401_dc1_initialization_check_capability, .build.declarative = dcn401_build_dc1_initialization, }; + static const struct bls_builder accelerated_mode_query_builder = { + .name = DCN_DECL_QUERY_ACCELERATED_MODE, + .kind = BLS_BUILDER_DECLARATIVE, + .build.declarative = dcn401_build_accelerated_mode_query, + }; switch (name) { case DCN_DECL_INITIALIZATION: @@ -411,6 +441,8 @@ const struct bls_builder *dcn401_bls_builder_create( return dcn401_non_seamless_commit_builder(); case DCN_DECL_SEAMLESS_UPDATE: return dcn401_seamless_update_builder(); + case DCN_DECL_QUERY_ACCELERATED_MODE: + return &accelerated_mode_query_builder; default: return NULL; } diff --git a/drivers/gpu/drm/amd/display/dc/core2/dc_core2.c b/drivers/gpu/drm/amd/display/dc/core2/dc_core2.c index 052f29df1797..295d2d8b277e 100644 --- a/drivers/gpu/drm/amd/display/dc/core2/dc_core2.c +++ b/drivers/gpu/drm/amd/display/dc/core2/dc_core2.c @@ -53,20 +53,6 @@ void core2_destruct(struct dc *dc) (void)dc; } -/* - * The VBIOS scratch read legacy_commit_state_hw makes - * before it enables accelerated mode. The commit has no accelerated-mode - * entries, so it runs only after init has left VBIOS mode. Remove when a - * BLC exposes the accelerated-mode bit. - */ -static bool core2_is_accelerated_mode(struct dc *dc) -{ - struct dc_bios *dcb = dc->ctx->dc_bios; - - return dcb && dcb->funcs && dcb->funcs->is_accelerated_mode && - dcb->funcs->is_accelerated_mode(dcb); -} - static struct pipe_ctx *core2_otg_master(struct dc_state *state) { unsigned int i; @@ -105,6 +91,43 @@ static bool core2_run_commit_sequence(struct dc *dc, result == DC2_BLS_EXEC_CONTINUED_ON_ERROR; } +/* + * legacy_commit_state_hw reads this bit before it enables accelerated + * mode. The commit and the update have no accelerated-mode entries, so + * they run only after init has left VBIOS mode. + */ +static bool core2_query_accelerated_mode(struct dc *dc) +{ + const struct bls_builder *builder = + TO_DC2(dc)->builders[DCN_DECL_QUERY_ACCELERATED_MODE]; + const struct workaround_manager *wam = dc2_workaround_manager_get(); + struct bls_builder_output_targets out_targets = {0}; + struct bls_builder_declarative_params *params; + bool accelerated_mode = false; + + if (!builder || builder->kind != BLS_BUILDER_DECLARATIVE || + !builder->build.declarative || !wam) + return false; + + /* 256 block-sequence entries; keep them off the kernel stack. */ + params = kvzalloc(sizeof(*params), GFP_KERNEL); + if (!params) + return false; + params->dc = dc; + params->current_state = dc->current_state; + out_targets.DCN_DECL_QUERY_ACCELERATED_MODE = &accelerated_mode; + params->out_targets = &out_targets; + + if (builder->build.declarative(params) != BLS_BUILD_SUCCESS || + params->tail_num_steps || + !core2_run_commit_sequence(dc, builder, wam, + params->head_sequence, ¶ms->head_num_steps)) + accelerated_mode = false; + + kvfree(params); + return accelerated_mode; +} + /* * dcn401_prepare_bandwidth's optimized_required writes. The Executor ORs * in the watermark and arbiter results. @@ -196,7 +219,7 @@ static bool core2_builder_supports(struct dc *dc, enum bls_builder_name name, builder->build.declarative && dc2_workaround_manager_get() && builder->check_capability(&check) && - core2_is_accelerated_mode(dc); + core2_query_accelerated_mode(dc); } /* Never falls back to legacy_commit_state_hw: DC2 must not call DC1. */ -- 2.43.0