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Tue, 10 Nov 2026 19:42:40 -0600 From: Wayne Lin To: CC: Harry Wentland , Leo Li , Aurabindo Pillai , Roman Li , Wayne Lin , Tom Chung , "Fangzhi Zuo" , Dan Wheeler , Ray Wu , Ivan Lipski , Alex Hung , James Lin , Chenyu Chen , Ray Wu , Hugo Sales Subject: [PATCH 37/74] drm/amd/display: Allow DC_PSR_MASK to enable PSR without DMUB PSR cap Date: Wed, 11 Nov 2026 09:28:43 +0800 Message-ID: <20261111014100.3596072-38-Wayne.Lin@amd.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20261111014100.3596072-1-Wayne.Lin@amd.com> References: <20261111014100.3596072-1-Wayne.Lin@amd.com> X-Archived-By: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN2PEPF0000A7FE:EE_|LV3PR12MB9404:EE_ X-MS-Office365-Filtering-Correlation-Id: 90f8018d-20ab-41cc-b19c-08df3f951835 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|82310400026|36860700016|1800799024|23010399003|376014|11063799006|56012099006|22082099003|18002099003|10067099003|261009223027099003|261026121527099003|261102123227099003|261021121427099003|261021123027099003; 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DCN 1.x, 2.x and 3.0.1 never do, so PSR can no longer be enabled there even with amdgpu.dcfeaturemask=0x8. [How] Skip the DMUB PSR cap check when DC_PSR_MASK is set, and add a KUnit case for this path. Tested-by: Hugo Sales Cc: ChiaHsuan Chung Signed-off-by: Ray Wu Signed-off-by: Wayne Lin --- .../drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c | 3 +- .../amdgpu_dm/tests/amdgpu_dm_psr_test.c | 35 ++++++++++++++++++- 2 files changed, 36 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c index dbad0a6d3a2b..295b1c307fa3 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c @@ -111,7 +111,8 @@ bool amdgpu_dm_set_psr_caps(struct dc_link *link, struct amdgpu_dm_connector *ac /* Reset psr version first */ link->psr_settings.psr_version = DC_PSR_VERSION_UNSUPPORTED; - if (!dc->caps.dmub_caps.psr) + /* DCN IPs that never query DMUB feature caps rely on DC_PSR_MASK to opt in */ + if (!dc->caps.dmub_caps.psr && !(amdgpu_dc_feature_mask & DC_PSR_MASK)) return false; if (!(link->connector_signal & SIGNAL_TYPE_EDP)) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_psr_test.c b/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_psr_test.c index 0a484ea7c0e8..c084e4f85f95 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_psr_test.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_psr_test.c @@ -230,15 +230,47 @@ static void dm_test_set_psr_caps_no_dmub_psr(struct kunit *test) { struct dc_link *link = alloc_test_psr_caps_link(test); struct amdgpu_dm_connector *aconnector = alloc_test_aconnector(test); + unsigned int old_feature_mask; + bool ret; link->psr_settings.psr_version = DC_PSR_VERSION_1; link->ctx->dc->caps.dmub_caps.psr = false; - KUNIT_EXPECT_FALSE(test, amdgpu_dm_set_psr_caps(link, aconnector)); + old_feature_mask = amdgpu_dm_psr_get_dc_feature_mask(); + amdgpu_dm_psr_set_dc_feature_mask(old_feature_mask & ~DC_PSR_MASK); + + ret = amdgpu_dm_set_psr_caps(link, aconnector); + amdgpu_dm_psr_set_dc_feature_mask(old_feature_mask); + + KUNIT_EXPECT_FALSE(test, ret); KUNIT_EXPECT_EQ(test, link->psr_settings.psr_version, DC_PSR_VERSION_UNSUPPORTED); } +/** + * dm_test_set_psr_caps_feature_mask_no_dmub_psr() - DC_PSR_MASK opts in without DMUB PSR cap. + * @test: KUnit test context. + */ +static void dm_test_set_psr_caps_feature_mask_no_dmub_psr(struct kunit *test) +{ + struct dc_link *link = alloc_test_psr_caps_link(test); + struct amdgpu_dm_connector *aconnector = alloc_test_aconnector(test); + unsigned int old_feature_mask; + bool ret; + + link->ctx->dc->caps.dmub_caps.psr = false; + + old_feature_mask = amdgpu_dm_psr_get_dc_feature_mask(); + amdgpu_dm_psr_set_dc_feature_mask(old_feature_mask | DC_PSR_MASK); + + ret = amdgpu_dm_set_psr_caps(link, aconnector); + amdgpu_dm_psr_set_dc_feature_mask(old_feature_mask); + + KUNIT_EXPECT_TRUE(test, ret); + KUNIT_EXPECT_NE(test, link->psr_settings.psr_version, + DC_PSR_VERSION_UNSUPPORTED); +} + /** * dm_test_set_psr_caps_non_edp() - Only eDP links can enable PSR. * @test: KUnit test context. @@ -712,6 +744,7 @@ static struct kunit_case dm_psr_test_cases[] = { KUNIT_CASE(dm_test_set_psr_caps_null_link), KUNIT_CASE(dm_test_set_psr_caps_null_connector), KUNIT_CASE(dm_test_set_psr_caps_no_dmub_psr), + KUNIT_CASE(dm_test_set_psr_caps_feature_mask_no_dmub_psr), KUNIT_CASE(dm_test_set_psr_caps_non_edp), KUNIT_CASE(dm_test_set_psr_caps_disconnected), KUNIT_CASE(dm_test_set_psr_caps_no_dpcd_psr), -- 2.43.0