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Ip=[165.204.84.17]; Helo=[satlexmb08.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN2PEPF0000A805.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB9039 X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "amd-gfx" X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=4.0.1 X-Spam-Checker-Version: SpamAssassin 4.0.1 (2024-03-26) on aws-us-west-2-korg-listserv-alma10-1 From: Eric Bernstein why: DPP60 is shared by ASICs without a UPSP block. On those, UPSP register offsets are 0 but masks may be non-zero, causing writes to address 0. how: Gate UPSP register access in DPP60 on the CNVC_UPSP_MODE register offset instead of the field mask. Cc: Nicholas Kazlauskas Signed-off-by: Eric Bernstein Signed-off-by: Wayne Lin --- drivers/gpu/drm/amd/display/dc/dpp/dcn60/dcn60_dpp.c | 2 +- drivers/gpu/drm/amd/display/dc/dpp/dcn60/dcn60_dpp_dscl.c | 4 ++++ 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dpp/dcn60/dcn60_dpp.c b/drivers/gpu/drm/amd/display/dc/dpp/dcn60/dcn60_dpp.c index 2ba8218e2ac2..dfdbc539ac42 100644 --- a/drivers/gpu/drm/amd/display/dc/dpp/dcn60/dcn60_dpp.c +++ b/drivers/gpu/drm/amd/display/dc/dpp/dcn60/dcn60_dpp.c @@ -321,7 +321,7 @@ void dcn6_dpp_reset(struct dpp *dpp_base) struct dcn60_dpp *dpp = TO_DCN60_DPP(dpp_base); if (dpp->scl_data.upsp) { - if (dpp->tf_mask->UPSP_MODE) { + if (REG(CNVC_UPSP_MODE)) { // Reset dpp registers used for upsp, lls REG_WRITE(CNVC_UPSP_MODE, 0); REG_WRITE(PRE_CSC_MODE, 0); diff --git a/drivers/gpu/drm/amd/display/dc/dpp/dcn60/dcn60_dpp_dscl.c b/drivers/gpu/drm/amd/display/dc/dpp/dcn60/dcn60_dpp_dscl.c index d1a81e5616b3..b75eb2772799 100644 --- a/drivers/gpu/drm/amd/display/dc/dpp/dcn60/dcn60_dpp_dscl.c +++ b/drivers/gpu/drm/amd/display/dc/dpp/dcn60/dcn60_dpp_dscl.c @@ -288,6 +288,10 @@ void dpp60_dscl_program_upsp(struct dpp *dpp_base, { struct dcn60_dpp *dpp = TO_DCN60_DPP(dpp_base); + /* UPSP block is not present on all ASICs */ + if (!REG(CNVC_UPSP_MODE)) + return; + REG_SET_8(CNVC_UPSP_MODE, 0, UPSP_MODE, dscl_prog_data->upsp_mode, UPSP_V_NUM_TAPS, dscl_prog_data->upsp_v_num_taps, -- 2.43.0