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Ip=[165.204.84.17]; Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF0000020A.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ2PR12MB8845 X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "amd-gfx" X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=4.0.1 X-Spam-Checker-Version: SpamAssassin 4.0.1 (2024-03-26) on aws-us-west-2-korg-listserv-alma10-1 From: Austin Zheng [Why] The n-1 UTM model has 8 SOC operating points. It sets sop_count to 8 and fills sops[0] through sops[7]. Mode support copies latency and available bandwidth from the v3 constraint for one point. That constraint was taken from the alternate-pstate row, so its latency and urgent bandwidth did not match the idle row. [How] This change does not write sop_count. The v3 table length stays UTM_QOS_MODEL_V3_MAX_SOP_COUNT, which is 5. dcn6_v3_sop_table_get_sop_constraint_at_index() reads latency from sops[IDLE][index]. dml2_utm_soc_bb_dcn6_v3_build_sop_table() stores that row's urgent_bandwidth_KBps and nominal_bandwidth_KBps as the minimum urgent and non-urgent bandwidth. dcn6_v3_sop_table_is_bandwidth_supported_at_index() still compares the highest alternate-pstate row as well. Cc: Dillon Varone Signed-off-by: Austin Zheng Signed-off-by: Wayne Lin --- .../dml2_utm_soc_bb/dml2_utm_soc_bb_dcn6.c | 19 +++++++++++++------ 1 file changed, 13 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_utm_soc_bb/dml2_utm_soc_bb_dcn6.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_utm_soc_bb/dml2_utm_soc_bb_dcn6.c index 586618d7dd58..7a1b2492969e 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_utm_soc_bb/dml2_utm_soc_bb_dcn6.c +++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_utm_soc_bb/dml2_utm_soc_bb_dcn6.c @@ -157,8 +157,9 @@ static void dcn6_v3_sop_table_get_sop_constraint_at_index(const struct dml2_sop_ unsigned int index, struct dml2_sop_constraint *constraint) { const struct utm_qos_model_dchub_v3 *dchub = table->model->dchub_v3; + // The mode support check is done based on the idle SOPs, not the active SOPs const struct utm_qos_model_dchub_v3_sop_entry *entry = - &dchub->sops[UTM_QOS_MODEL_V3_LOAD_LEVEL_ACTIVE_ALTERNATE_PSTATE][index]; + &dchub->sops[UTM_QOS_MODEL_V3_LOAD_LEVEL_IDLE][index]; DML_ASSERT_MSG(index < dchub->sop_count, "unsupported sop index\n"); constraint->dcn5.clocks.fclk_khz = 0; @@ -174,6 +175,8 @@ static void dcn6_v3_sop_table_get_sop_constraint_at_index(const struct dml2_sop_ constraint->dcn5.latency.dcn5.avg_req_latency_non_urg = entry->avg_req_latency_non_urg_ps / 1000000.0; constraint->dcn5.latency.dcn5.df_response_time_us = entry->df_response_time_ps / 1000000.0; constraint->dcn5.min_available_urgent_bandwidth_KBps = table->sop_min_available_urgent_bandwidths_KBps[index]; + // non urgent bandwidth needs to be plumbed for presentation in the spreadsheet + constraint->dcn5.min_available_non_urgent_bandwidth_KBps = table->sop_min_available_non_urgent_bandwidths_KBps[index]; constraint->dcn5.min_sop_index = index; } @@ -267,14 +270,18 @@ static void dml2_utm_soc_bb_dcn6_v3_build_sop_table(struct dml2_sop_table *table for (i = 0; i < dchub->sop_count; i++) { const struct utm_qos_model_dchub_v3_sop_entry *idle_entry = - &dchub->sops[UTM_QOS_MODEL_V3_LOAD_LEVEL_IDLE][i]; - const struct utm_qos_model_dchub_v3_sop_entry *active_entry = - &dchub->sops[UTM_QOS_MODEL_V3_LOAD_LEVEL_ACTIVE_ALTERNATE_PSTATE][i]; + &dchub->sops[UTM_QOS_MODEL_V3_LOAD_LEVEL_IDLE][i]; table->sop_optimal_dcfclks_khz[i] = - dcn6_v3_sop_table_calculate_optimal_dcfclk_khz(utm_soc_bb, idle_entry); + dcn6_v3_sop_table_calculate_optimal_dcfclk_khz(utm_soc_bb, idle_entry); + // The mode support check is done based on the idle SOPs, not the active SOPs table->sop_min_available_urgent_bandwidths_KBps[i] = - active_entry->urgent_bandwidth_KBps; + idle_entry->urgent_bandwidth_KBps; + // non urgent bandwidth needs to be plumbed for presentation in the spreadsheet + table->sop_min_available_non_urgent_bandwidths_KBps[i] = + idle_entry->nominal_bandwidth_KBps; + // TODO - remove min_available_urgent_bandwidth_KBps and move stutter efficiency calculation to populate informative. + } } -- 2.43.0