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Ip=[165.204.84.17]; Helo=[satlexmb08.amd.com] X-MS-Exchange-CrossTenant-AuthSource: EA8PEPF0000000B.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA3PR12MB7877 X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "amd-gfx" X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=4.0.1 X-Spam-Checker-Version: SpamAssassin 4.0.1 (2024-03-26) on aws-us-west-2-korg-listserv-alma10-1 From: Austin Zheng [Why/How] New parameter to track DPPs effectively in-use per-plane vs total number of DPPs assigned to a plane Cc: Dillon Varone Signed-off-by: Austin Zheng Signed-off-by: Wayne Lin --- .../src/dml2_core/dml2_core_dcn6_funcs_mode_programming.c | 5 +++-- .../src/dml2_core/dml2_core_dcn6_funcs_mode_support.c | 7 ++++--- .../dc/dml2_0/dml21/src/dml2_core/dml2_core_shared_types.h | 2 ++ 3 files changed, 9 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn6_funcs_mode_programming.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn6_funcs_mode_programming.c index 372691a263d5..0bec9baf809e 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn6_funcs_mode_programming.c +++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn6_funcs_mode_programming.c @@ -101,7 +101,7 @@ static void dcn6_mp_calculate_pixel_delivery_times(struct dml2_core_calculate_mp //Display Pipeline Delivery Time in Prefetch, Groups get_calcs(ctx)->calculate_pixel_delivery_times( display_cfg, - inputs->NoOfDPP, + inputs->effective_number_of_dpp, display_cfg->num_planes, inputs->VRatioPrefetchY, inputs->VRatioPrefetchC, @@ -403,7 +403,7 @@ static void dcn6_mp_calculate_stutter_efficiency(struct dml2_core_calculate_mp_c p->Z8StutterEnterPlusExitWatermark = inputs->Watermark.Z8StutterEnterPlusExitWatermark; p->ProgressiveToInterlaceUnitInOPP = ip->ptoi_supported; p->MinTTUVBlank = inputs->MinTTUVBlank; - p->DPPPerSurface = inputs->NoOfDPP; + p->DPPPerSurface = inputs->effective_number_of_dpp; p->DETBufferSizeY = inputs->DETBufferSizeY; p->BytePerPixelY = inputs->BytePerPixelY; p->BytePerPixelDETY = inputs->BytePerPixelInDETY; @@ -1079,6 +1079,7 @@ void dcn6_mp_initialize_from_solution(struct dml2_core_internal_mode_program *ou outputs->immediate_flip_required = outputs->immediate_flip_required || plane->immediate_flip; outputs->NoOfDPP[k] = plane_support_info->dpps_used; + outputs->effective_number_of_dpp[k] = outputs->NoOfDPP[k]; outputs->dsc_enable[k] = stream_support_info->dsc_enable; outputs->num_dsc_slices[k] = stream_support_info->num_dsc_slices; } diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn6_funcs_mode_support.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn6_funcs_mode_support.c index c1cb43386473..ef56428d373e 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn6_funcs_mode_support.c +++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn6_funcs_mode_support.c @@ -1018,6 +1018,7 @@ static void dcn6_ms_calculate_num_of_dpp_required( outputs->NoOfDPP[k] = 2; } } + outputs->effective_number_of_dpp[k] = outputs->NoOfDPP[k]; DML_LOG_VERBOSE("DML::%s: k=%d, NoOfDPP = %d\n", __func__, k, outputs->NoOfDPP[k]); } @@ -2205,7 +2206,7 @@ void dcn6_ms_calculate_min_dcfclk_deepsleep_clock( inputs->BytePerPixelC, inputs->SwathWidthY, inputs->SwathWidthC, - inputs->NoOfDPP, + inputs->effective_number_of_dpp, inputs->PSCL_FACTOR, inputs->PSCL_FACTOR_CHROMA, inputs->RequiredDPPCLK, @@ -2742,7 +2743,7 @@ void dcn6_ms_calculate_urgent_latency( ip->pixel_chunk_size_kbytes, inputs->min_available_urgent_bandwidth_MBps, display_cfg->num_planes, - inputs->NoOfDPP, + inputs->effective_number_of_dpp, inputs->dpte_group_bytes, inputs->tdlut_bytes_per_group, inputs->HostVMInefficiencyFactor, @@ -3781,7 +3782,7 @@ void dcn6_ms_calculate_watermarks( //CalculateWatermarks_params->LBBitPerPixel = 57; // FIXME_STAGE2, need a new ip param? p->SwathWidthY = inputs->SwathWidthY; p->SwathWidthC = inputs->SwathWidthC; - p->DPPPerSurface = inputs->NoOfDPP; + p->DPPPerSurface = inputs->effective_number_of_dpp; p->BytePerPixelDETY = inputs->BytePerPixelInDETY; p->BytePerPixelDETC = inputs->BytePerPixelInDETC; p->DSTXAfterScaler = inputs->DSTXAfterScaler; diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_shared_types.h b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_shared_types.h index 4848dbffc184..dbc59c308762 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_shared_types.h +++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_shared_types.h @@ -586,6 +586,7 @@ struct dml2_core_internal_mode_support { double surface_avg_vactive_required_bw[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max][DML2_MAX_PLANES]; double surface_peak_required_bw[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max][DML2_MAX_PLANES]; + unsigned int effective_number_of_dpp[DML2_MAX_PLANES]; // Something that should be feedback to caller enum dml2_odm_mode ODMMode[DML2_MAX_PLANES]; unsigned int SurfaceSizeInMALL[DML2_MAX_PLANES]; @@ -779,6 +780,7 @@ struct dml2_core_internal_mode_program { double prefetch_vmrow_bw[DML2_MAX_PLANES]; double cursor_bw[DML2_MAX_PLANES]; double prefetch_cursor_bw[DML2_MAX_PLANES]; + unsigned int effective_number_of_dpp[DML2_MAX_PLANES]; double WritebackDelay[DML2_MAX_PLANES]; unsigned int dpte_row_height[DML2_MAX_PLANES]; unsigned int dpte_row_height_linear[DML2_MAX_PLANES]; -- 2.43.0