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Tue, 10 Nov 2026 19:45:01 -0600 From: Wayne Lin To: CC: Harry Wentland , Leo Li , Aurabindo Pillai , Roman Li , Wayne Lin , Tom Chung , "Fangzhi Zuo" , Dan Wheeler , Ray Wu , Ivan Lipski , Alex Hung , James Lin , Chenyu Chen , Sridevi Arvindekar , Alvin Lee Subject: [PATCH 65/74] drm/amd/display: Bypass chroma upsampling without the DPP cap Date: Wed, 11 Nov 2026 09:29:11 +0800 Message-ID: <20261111014100.3596072-66-Wayne.Lin@amd.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20261111014100.3596072-1-Wayne.Lin@amd.com> References: <20261111014100.3596072-1-Wayne.Lin@amd.com> X-Archived-By: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: EA8PEPF00000008:EE_|IA4PR12MB469045:EE_ X-MS-Office365-Filtering-Correlation-Id: a48084aa-014b-45f1-1393-08df3f956928 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|376014|82310400026|23010399003|1800799024|36860700016|261009223027099003|10067099003|261102123227099003|261026121527099003|261021123027099003|261021121427099003|56012099006|11063799006|22082099003|18002099003; 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The scaler input forced bypass only for DCN 4.01, 4.2 and 4.2B. [How] resource_is_upsp_required() returns UPSP_BYPASS when caps.color.dpp.upsp_pre_scaler is 0. Only DCN6 sets that cap. translate_SPL_in_params_from_pipe_ctx() copies scl_data.upsp for every ASIC. Cc: Alvin Lee Signed-off-by: Sridevi Arvindekar Signed-off-by: Wayne Lin --- .../amd/display/dc/bls_builder/dcn401_seamless_builder.c | 2 +- drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c | 2 +- drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 2 +- drivers/gpu/drm/amd/display/dc/core/dc_resource_helper.c | 7 ++++++- drivers/gpu/drm/amd/display/dc/dc_spl_translate.c | 8 ++++---- drivers/gpu/drm/amd/display/dc/inc/resource.h | 3 ++- 6 files changed, 15 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/bls_builder/dcn401_seamless_builder.c b/drivers/gpu/drm/amd/display/dc/bls_builder/dcn401_seamless_builder.c index 23951ef4fe04..8a563386d725 100644 --- a/drivers/gpu/drm/amd/display/dc/bls_builder/dcn401_seamless_builder.c +++ b/drivers/gpu/drm/amd/display/dc/bls_builder/dcn401_seamless_builder.c @@ -1789,7 +1789,7 @@ static void dcn401_add_step(struct block_sequence_state *sequence, plane->input_csc_color_matrix; p->setup_dpp_params.color_space = plane->color_space; p->setup_dpp_params.upsp_mode = resource_is_upsp_required( - plane->format, plane->scaling_linearity); + (bool) plane->ctx->dc->caps.color.dpp.upsp_pre_scaler, plane->format, plane->scaling_linearity); break; case DPP_SET_CURSOR_MATRIX: p->dpp_set_cursor_matrix_params.dpp = dpp; diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c index c5e8a88d051d..82ac4ca4a13b 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c @@ -5793,7 +5793,7 @@ void hwss_add_dpp_setup_dpp(struct block_sequence_state *seq_state, p->format = plane_state->format; p->input_csc_color_matrix = plane_state->input_csc_color_matrix; p->color_space = plane_state->color_space; - p->upsp_mode = resource_is_upsp_required(plane_state->format, plane_state->scaling_linearity); + p->upsp_mode = resource_is_upsp_required((bool)plane_state->ctx->dc->caps.color.dpp.upsp_pre_scaler, plane_state->format, plane_state->scaling_linearity); (*seq_state->num_steps)++; } } diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c index 3e87ec8ad6a5..2240afde4089 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c @@ -1608,7 +1608,7 @@ bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx) pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_30BPP; pipe_ctx->plane_res.scl_data.lb_params.alpha_en = plane_state->per_pixel_alpha; - pipe_ctx->plane_res.scl_data.upsp = resource_is_upsp_required(plane_state->format, plane_state->scaling_linearity); + pipe_ctx->plane_res.scl_data.upsp = resource_is_upsp_required((bool)plane_state->ctx->dc->caps.color.dpp.upsp_pre_scaler, plane_state->format, plane_state->scaling_linearity); // Convert pipe_ctx to respective input params for SPL translate_SPL_in_params_from_pipe_ctx(pipe_ctx, spl_in); diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource_helper.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource_helper.c index 55dfa465163f..d3987be3ce39 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_resource_helper.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource_helper.c @@ -26,9 +26,14 @@ #include "sspl/dc_spl_types.h" #include "resource.h" -enum upsp_mode resource_is_upsp_required(enum surface_pixel_format format, +enum upsp_mode resource_is_upsp_required(bool upsp_pre_scaler, + enum surface_pixel_format format, enum dc_scaling_linearity scaling_linearity) { + /* UPSP is not supported on all ASICs */ + if (!upsp_pre_scaler) + return UPSP_BYPASS; + bool scaling_in_linear = (scaling_linearity == DC_SCALING_LINEARITY_LINEAR); bool is_420_format = (format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN && format <= SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb); diff --git a/drivers/gpu/drm/amd/display/dc/dc_spl_translate.c b/drivers/gpu/drm/amd/display/dc/dc_spl_translate.c index 00e121bb8ef7..1b7f0ee6ba97 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_spl_translate.c +++ b/drivers/gpu/drm/amd/display/dc/dc_spl_translate.c @@ -211,19 +211,19 @@ void translate_SPL_in_params_from_pipe_ctx(struct pipe_ctx *pipe_ctx, struct spl // Translate linear light scaling preference if (pipe_ctx->stream->ctx->dc->debug.force_lls > 0) { spl_in->lls_pref = pipe_ctx->stream->ctx->dc->debug.force_lls; - spl_in->upsp_mode = pipe_ctx->plane_res.scl_data.upsp; } else { if ((plane_state->ctx->dce_version == DCN_VERSION_4_01) || (plane_state->ctx->dce_version == DCN_VERSION_4_2) || (plane_state->ctx->dce_version == DCN_VERSION_4_2B)) { spl_in->lls_pref = LLS_PREF_DONT_CARE; - spl_in->upsp_mode = UPSP_BYPASS; } else { set_linear_light_scaling_preference(plane_state, spl_in); - /* Translate upsampling mode*/ - spl_in->upsp_mode = pipe_ctx->plane_res.scl_data.upsp; } } + + /* Translate upsampling mode*/ + spl_in->upsp_mode = pipe_ctx->plane_res.scl_data.upsp; + /* Translate chroma subsampling offset ( cositing ) */ if (pipe_ctx->stream->ctx->dc->debug.force_cositing) { spl_in->basic_in.cositing = pipe_ctx->stream->ctx->dc->debug.force_cositing - 1; diff --git a/drivers/gpu/drm/amd/display/dc/inc/resource.h b/drivers/gpu/drm/amd/display/dc/inc/resource.h index 0d9c9771ea7c..fbd874476aaf 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/resource.h +++ b/drivers/gpu/drm/amd/display/dc/inc/resource.h @@ -123,7 +123,8 @@ void resource_build_test_pattern_params( struct resource_context *res_ctx, struct pipe_ctx *pipe_ctx); -enum upsp_mode resource_is_upsp_required(enum surface_pixel_format format, +enum upsp_mode resource_is_upsp_required(bool upsp_pre_scaler, + enum surface_pixel_format format, enum dc_scaling_linearity scaling_linearity); bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx); -- 2.43.0