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[94.27.152.162]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-488fc0f8193sm259871165e9.1.2026.04.20.06.49.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Apr 2026 06:49:59 -0700 (PDT) From: Timur =?UTF-8?B?S3Jpc3TDs2Y=?= To: amd-gfx@lists.freedesktop.org, alexander.deucher@amd.com, Christian =?UTF-8?B?S8O2bmln?= Subject: Re: [PATCH 3/7] drm/amdgpu/vce1: Correct firmware offset mask Date: Mon, 20 Apr 2026 15:49:58 +0200 Message-ID: <2216811.9o76ZdvQCi@timur-hyperion> In-Reply-To: <14b58bb8-e1bf-4b9d-9957-dbdc32144278@amd.com> References: <20260420121044.155030-1-timur.kristof@gmail.com> <20260420121044.155030-4-timur.kristof@gmail.com> <14b58bb8-e1bf-4b9d-9957-dbdc32144278@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" On Monday, April 20, 2026 2:23:18=E2=80=AFPM Central European Summer Time C= hristian=20 K=C3=B6nig wrote: > On 4/20/26 14:10, Timur Krist=C3=B3f wrote: > > It's 0x0fffffff and not 0x7fffffff. > >=20 > > Fixes: d4a640d4b9f3 ("drm/amdgpu/vce1: Implement VCE1 IP block (v2)") > > Signed-off-by: Timur Krist=C3=B3f > > --- > >=20 > > drivers/gpu/drm/amd/amdgpu/vce_v1_0.c | 8 ++++---- > > 1 file changed, 4 insertions(+), 4 deletions(-) > >=20 > > diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v1_0.c > > b/drivers/gpu/drm/amd/amdgpu/vce_v1_0.c index > > 2fe931366985a..ce993b57b0e9f 100644 > > --- a/drivers/gpu/drm/amd/amdgpu/vce_v1_0.c > > +++ b/drivers/gpu/drm/amd/amdgpu/vce_v1_0.c > > @@ -313,17 +313,17 @@ static int vce_v1_0_mc_resume(struct amdgpu_device > > *adev)>=20 > > offset =3D adev->vce.gpu_addr + AMDGPU_VCE_FIRMWARE_OFFSET; > > size =3D VCE_V1_0_FW_SIZE; > >=20 > > - WREG32(mmVCE_VCPU_CACHE_OFFSET0, offset & 0x7fffffff); > > + WREG32(mmVCE_VCPU_CACHE_OFFSET0, offset & 0x0fffffff); > >=20 > > WREG32(mmVCE_VCPU_CACHE_SIZE0, size); > > =09 > > offset +=3D size; > > size =3D VCE_V1_0_STACK_SIZE; > >=20 > > - WREG32(mmVCE_VCPU_CACHE_OFFSET1, offset & 0x7fffffff); > > + WREG32(mmVCE_VCPU_CACHE_OFFSET1, offset & 0x0fffffff); > >=20 > > WREG32(mmVCE_VCPU_CACHE_SIZE1, size); > > =09 > > offset +=3D size; > > size =3D VCE_V1_0_DATA_SIZE; > >=20 > > - WREG32(mmVCE_VCPU_CACHE_OFFSET2, offset & 0x7fffffff); > > + WREG32(mmVCE_VCPU_CACHE_OFFSET2, offset & 0x0fffffff); >=20 > We actually have that as VCE_VCPU_CACHE_OFFSET*__OFFSET_MASK in the heade= rs, > would probably be a good idea to use that one instead. >=20 > Additional to that limiting the value actually doesn't make much sense, t= hat > just hides the problem when we really get an offset which is to large. >=20 > We should probably rather have a WARN_ON(offset & > ~VCE_VCPU_CACHE_OFFSET2__OFFSET_MASK) directly above the register write. >=20 > Apart from that the patch looks good to me. >=20 > Regards, > Christian. Hi Christian, Thanks, I agree and I'll add the necessary changes. That being said, with some further testing it seems that VCE fails to=20 initialize when the gpu_addr is 128 MiB or more, which makes me think that = we=20 should use 0x07ffffff instead of 0x0fffffff. Does that sound reasonable to = you? Thanks, Timur >=20 > > WREG32(mmVCE_VCPU_CACHE_SIZE2, size); > > =09 > > WREG32_P(mmVCE_LMI_CTRL2, 0x0, ~0x100); > >=20 > > @@ -531,7 +531,7 @@ static int vce_v1_0_early_init(struct amdgpu_ip_blo= ck > > *ip_block)>=20 > > static int vce_v1_0_ensure_vcpu_bo_32bit_addr(struct amdgpu_device *ad= ev) > > { > > =20 > > u64 bo_size =3D amdgpu_bo_size(adev->vce.vcpu_bo); > >=20 > > - u64 max_vcpu_bo_addr =3D 0xffffffff - bo_size; > > + u64 max_vcpu_bo_addr =3D 0x0fffffff - bo_size; > >=20 > > u64 num_pages =3D ALIGN(bo_size, AMDGPU_GPU_PAGE_SIZE) / > > AMDGPU_GPU_PAGE_SIZE; u64 pa =3D amdgpu_gmc_vram_pa(adev, > > adev->vce.vcpu_bo); > > u64 flags =3D AMDGPU_PTE_READABLE | AMDGPU_PTE_WRITEABLE | > > AMDGPU_PTE_VALID;