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Wed, 7 May 2025 15:27:42 +0000 Message-ID: <2227b521-3f4e-41de-90ef-fe3d2d031c67@amd.com> Date: Wed, 7 May 2025 11:27:40 -0400 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 1/7] Revert "drm/amdgpu: Use generic hdp flush function" To: Alex Deucher , Alex Deucher Cc: amd-gfx@lists.freedesktop.org References: <20250505130459.1985637-1-alexander.deucher@amd.com> Content-Language: en-US From: Felix Kuehling In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-ClientProxiedBy: YQZPR01CA0094.CANPRD01.PROD.OUTLOOK.COM (2603:10b6:c01:84::22) To BN9PR12MB5115.namprd12.prod.outlook.com (2603:10b6:408:118::14) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN9PR12MB5115:EE_|DM4PR12MB6565:EE_ X-MS-Office365-Filtering-Correlation-Id: bc140268-6696-41bd-eb27-08dd8d7bb583 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|1800799024|366016; X-Microsoft-Antispam-Message-Info: =?utf-8?B?RWM0MkQ2MCtmc0t0OUVtbDZKcm9aZ1BjTUQ2ZFdoUUoxQUVyK1AvZk9TRlVH?= =?utf-8?B?ek1qRHFzNlE3YVJ4NGVQWXczVzJQR3NIeGNQTFJiMldZQk1YaXc4akdlUDAx?= =?utf-8?B?MDNDY3dvd29oMUdNL2kzLzY2N3pUNS9TZ0FVS3cwS0pqNDhpb0t0UXVDdERK?= =?utf-8?B?THZBMVFFY29WS3Fnd0NaWWxEZnVXR2FZRlNDU0JZdEFaRTJ2ZEgzZFlFdFYy?= =?utf-8?B?UGF1MHRwRHBUYld6cytFcnF1dzJyQlZLWkM1bXJtOTJVOHVKZ2RtZFF0bmNP?= =?utf-8?B?Q3JiK082cE1oenlhdnltdXlSYzhZNW1mZk5TOG9laFloVWtKOFRmMHdieisx?= =?utf-8?B?MGJDYmpXZUpJamIyRmNTcEFjdndpTlJVejlxNTBBZGpzWHRYM1J4OW1valNK?= =?utf-8?B?cFprZ3g4clNOT0dZMUFzdGhjOENvS2dNa3dvUGNJbHVMRmRod25WOGU4OG03?= =?utf-8?B?VkxOWld5T1F2NzVObnZOMlJBY29DejV2Y0dSdFBiSEF1dE1JSVBRR0JnOXlm?= =?utf-8?B?Y2pQSUxIT1Z1RElWaktEOHF1NHFJMjBQM1RTeStkbnZPRm0rOXFLZmJPTXRq?= =?utf-8?B?OFRFaHMxenpnZGRzQ2xSVENBekZvbmN0OVFHU1Q2QU53cHB4UXprbEE0ZHl5?= =?utf-8?B?d1dtKzIzVmw1KzFDN3U3U3JIVmx5ZHBnQ0RXTG0xNG13b1hDSG1nTlBtMnZa?= =?utf-8?B?VGV0c2FlakdrYmJEY0JZTHhKbC9mK1hCanMrVTBSdTVNejYrNmdqRGgxMjdX?= =?utf-8?B?bjgzOEFOZkttQURZcWJGNVJrVVBseG9YeG5zOWNJWkVmVXdmVGQvakRURkE3?= =?utf-8?B?amlGVnJYdFVSS1NGTVlUY1llcXF2Z3JEQXhLdEJVa1V1WUpnVmV5dTNZdlhJ?= =?utf-8?B?SUp3KzVHRFF5WnBvRGEyWHNmWUdNNnMyWGk3RnBxeVlLY3B6c1poMS9BN0VF?= =?utf-8?B?V01jRXlpOEZwdjI1cTl5OEErdCs0WkhhWkVlcmVKMldWVWVYcXU4T0p0dnpv?= =?utf-8?B?UzVidDdwcGNvRzE3UkFLbmt6K09YcUlqbzRYdjdBL2M2NENGdmlmQ3BsbEFL?= =?utf-8?B?ZDNpN1V2VXozT2V6VUNQSjdmYkJZbThVNDlQVWZ1aHI1WXBDRVdQNlFlOUVB?= =?utf-8?B?MmlPSGNRdURjNWlwUnFsQnhsV1M2ZGMySDNZZC9xalAvQ0xQK3ByL3JRWjRN?= =?utf-8?B?ZFcvZGZrbjRCcDlxZ3A2eS9vdG5aNFdCMFk4UHJUVG5CV1p6WTUzOGUrRlRR?= =?utf-8?B?ZWlMeE9pS0hBK0gvSy9FL2hSTTRYS3ZENVdPSkR3S3RtNjlPc2twRW1UWnZs?= =?utf-8?B?N3NZWHgyYUdWMDNiTzloV2ZNM1hmQS94ZzRvdVI1UFlhRHlTZmNRT3IvV0pC?= =?utf-8?B?UTc2aGJWTE1Va1lxTjBmSS9pdTVKYkJvSVJGSmg0MDY0Z2dYYThOZVkyb1FJ?= =?utf-8?B?di9yWHlsK1dsWWU1RDBlWVRucVFUaDVOaTgyaEsveHZqRkt5S2phd1lQcWFM?= =?utf-8?B?UVJXcTVhb1hIODNSY3l5bFU5MmJ2RWlId0E2ang3UG9teTVTZGRRcVVFMUJ6?= =?utf-8?B?UTFFc0FnZVU0Y2owY3ZneTVGcVNwdnYzbmlkc2pRM1BWTVhZdnd3bnBhTnc2?= =?utf-8?B?K3JXMnJ3b29vYjFQcjdOcHhlRXNEd1BJUitmK3FRWC9IWFlPRDY2NExET1Bk?= =?utf-8?B?T3MvSnZ5RUd2Z3RUbWRLeFQ5NUV0dHpWUFRGSXd3eEt2QnNuSXR5N25Ma2sz?= =?utf-8?B?SHEzd3ZhNm15bGs4QmpoVXN3Vml1MzRPK0FvRjlubUJuNzYxM29sOWVDaU05?= =?utf-8?B?bUFYWWlXNkZ3TklNR1Y2MnhUWGJQTEZ6NmhGTm5lQStUZmF1dVlxelh3aHVs?= =?utf-8?B?M0hnbkVGS296a251UUpUL0o5Z1VrWnVQNW1BR1ZaRFBoU0R1ZXRlUEUzbzR3?= =?utf-8?Q?IU3zgvlrTn0=3D?= X-Forefront-Antispam-Report: CIP:255.255.255.255; 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This fixes a regression. > > Alex > > On Mon, May 5, 2025 at 9:05 AM Alex Deucher wrote: >> This reverts commit 18a878fd8aef0ec21648a3782f55a79790cd4073. >> >> Revert this temporarily to make it easier to fix a regression >> in the HDP handling. >> >> Signed-off-by: Alex Deucher The series is Reviewed-by: Felix Kuehling >> --- >> drivers/gpu/drm/amd/amdgpu/amdgpu_hdp.c | 21 --------------------- >> drivers/gpu/drm/amd/amdgpu/amdgpu_hdp.h | 2 -- >> drivers/gpu/drm/amd/amdgpu/hdp_v4_0.c | 13 ++++++++++++- >> drivers/gpu/drm/amd/amdgpu/hdp_v5_0.c | 13 ++++++++++++- >> drivers/gpu/drm/amd/amdgpu/hdp_v6_0.c | 13 ++++++++++++- >> drivers/gpu/drm/amd/amdgpu/hdp_v7_0.c | 13 ++++++++++++- >> 6 files changed, 48 insertions(+), 27 deletions(-) >> >> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_hdp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_hdp.c >> index 7fd8f09c28e66..b6cf801939aa5 100644 >> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_hdp.c >> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_hdp.c >> @@ -22,7 +22,6 @@ >> */ >> #include "amdgpu.h" >> #include "amdgpu_ras.h" >> -#include >> >> int amdgpu_hdp_ras_sw_init(struct amdgpu_device *adev) >> { >> @@ -47,23 +46,3 @@ int amdgpu_hdp_ras_sw_init(struct amdgpu_device *adev) >> /* hdp ras follows amdgpu_ras_block_late_init_default for late init */ >> return 0; >> } >> - >> -void amdgpu_hdp_generic_flush(struct amdgpu_device *adev, >> - struct amdgpu_ring *ring) >> -{ >> - if (!ring || !ring->funcs->emit_wreg) { >> - WREG32((adev->rmmio_remap.reg_offset + >> - KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> >> - 2, >> - 0); >> - RREG32((adev->rmmio_remap.reg_offset + >> - KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> >> - 2); >> - } else { >> - amdgpu_ring_emit_wreg(ring, >> - (adev->rmmio_remap.reg_offset + >> - KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> >> - 2, >> - 0); >> - } >> -} >> \ No newline at end of file >> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_hdp.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_hdp.h >> index 4cfd932b7e91e..7b8a6152dc8d9 100644 >> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_hdp.h >> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_hdp.h >> @@ -44,6 +44,4 @@ struct amdgpu_hdp { >> }; >> >> int amdgpu_hdp_ras_sw_init(struct amdgpu_device *adev); >> -void amdgpu_hdp_generic_flush(struct amdgpu_device *adev, >> - struct amdgpu_ring *ring); >> #endif /* __AMDGPU_HDP_H__ */ >> diff --git a/drivers/gpu/drm/amd/amdgpu/hdp_v4_0.c b/drivers/gpu/drm/amd/amdgpu/hdp_v4_0.c >> index e6c0d86d34865..f1dc13b3ab38e 100644 >> --- a/drivers/gpu/drm/amd/amdgpu/hdp_v4_0.c >> +++ b/drivers/gpu/drm/amd/amdgpu/hdp_v4_0.c >> @@ -36,6 +36,17 @@ >> #define HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK 0x00020000L >> #define mmHDP_MEM_POWER_CTRL_BASE_IDX 0 >> >> +static void hdp_v4_0_flush_hdp(struct amdgpu_device *adev, >> + struct amdgpu_ring *ring) >> +{ >> + if (!ring || !ring->funcs->emit_wreg) { >> + WREG32((adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0); >> + RREG32((adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2); >> + } else { >> + amdgpu_ring_emit_wreg(ring, (adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0); >> + } >> +} >> + >> static void hdp_v4_0_invalidate_hdp(struct amdgpu_device *adev, >> struct amdgpu_ring *ring) >> { >> @@ -169,7 +180,7 @@ struct amdgpu_hdp_ras hdp_v4_0_ras = { >> }; >> >> const struct amdgpu_hdp_funcs hdp_v4_0_funcs = { >> - .flush_hdp = amdgpu_hdp_generic_flush, >> + .flush_hdp = hdp_v4_0_flush_hdp, >> .invalidate_hdp = hdp_v4_0_invalidate_hdp, >> .update_clock_gating = hdp_v4_0_update_clock_gating, >> .get_clock_gating_state = hdp_v4_0_get_clockgating_state, >> diff --git a/drivers/gpu/drm/amd/amdgpu/hdp_v5_0.c b/drivers/gpu/drm/amd/amdgpu/hdp_v5_0.c >> index 8bc001dc9f631..43195c0797480 100644 >> --- a/drivers/gpu/drm/amd/amdgpu/hdp_v5_0.c >> +++ b/drivers/gpu/drm/amd/amdgpu/hdp_v5_0.c >> @@ -27,6 +27,17 @@ >> #include "hdp/hdp_5_0_0_sh_mask.h" >> #include >> >> +static void hdp_v5_0_flush_hdp(struct amdgpu_device *adev, >> + struct amdgpu_ring *ring) >> +{ >> + if (!ring || !ring->funcs->emit_wreg) { >> + WREG32((adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0); >> + RREG32((adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2); >> + } else { >> + amdgpu_ring_emit_wreg(ring, (adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0); >> + } >> +} >> + >> static void hdp_v5_0_invalidate_hdp(struct amdgpu_device *adev, >> struct amdgpu_ring *ring) >> { >> @@ -206,7 +217,7 @@ static void hdp_v5_0_init_registers(struct amdgpu_device *adev) >> } >> >> const struct amdgpu_hdp_funcs hdp_v5_0_funcs = { >> - .flush_hdp = amdgpu_hdp_generic_flush, >> + .flush_hdp = hdp_v5_0_flush_hdp, >> .invalidate_hdp = hdp_v5_0_invalidate_hdp, >> .update_clock_gating = hdp_v5_0_update_clock_gating, >> .get_clock_gating_state = hdp_v5_0_get_clockgating_state, >> diff --git a/drivers/gpu/drm/amd/amdgpu/hdp_v6_0.c b/drivers/gpu/drm/amd/amdgpu/hdp_v6_0.c >> index ec20daf4272c5..a88d25a06c29b 100644 >> --- a/drivers/gpu/drm/amd/amdgpu/hdp_v6_0.c >> +++ b/drivers/gpu/drm/amd/amdgpu/hdp_v6_0.c >> @@ -30,6 +30,17 @@ >> #define regHDP_CLK_CNTL_V6_1 0xd5 >> #define regHDP_CLK_CNTL_V6_1_BASE_IDX 0 >> >> +static void hdp_v6_0_flush_hdp(struct amdgpu_device *adev, >> + struct amdgpu_ring *ring) >> +{ >> + if (!ring || !ring->funcs->emit_wreg) { >> + WREG32((adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0); >> + RREG32((adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2); >> + } else { >> + amdgpu_ring_emit_wreg(ring, (adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0); >> + } >> +} >> + >> static void hdp_v6_0_update_clock_gating(struct amdgpu_device *adev, >> bool enable) >> { >> @@ -138,7 +149,7 @@ static void hdp_v6_0_get_clockgating_state(struct amdgpu_device *adev, >> } >> >> const struct amdgpu_hdp_funcs hdp_v6_0_funcs = { >> - .flush_hdp = amdgpu_hdp_generic_flush, >> + .flush_hdp = hdp_v6_0_flush_hdp, >> .update_clock_gating = hdp_v6_0_update_clock_gating, >> .get_clock_gating_state = hdp_v6_0_get_clockgating_state, >> }; >> diff --git a/drivers/gpu/drm/amd/amdgpu/hdp_v7_0.c b/drivers/gpu/drm/amd/amdgpu/hdp_v7_0.c >> index ed1debc035073..49f7eb4fbd117 100644 >> --- a/drivers/gpu/drm/amd/amdgpu/hdp_v7_0.c >> +++ b/drivers/gpu/drm/amd/amdgpu/hdp_v7_0.c >> @@ -27,6 +27,17 @@ >> #include "hdp/hdp_7_0_0_sh_mask.h" >> #include >> >> +static void hdp_v7_0_flush_hdp(struct amdgpu_device *adev, >> + struct amdgpu_ring *ring) >> +{ >> + if (!ring || !ring->funcs->emit_wreg) { >> + WREG32((adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0); >> + RREG32((adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2); >> + } else { >> + amdgpu_ring_emit_wreg(ring, (adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0); >> + } >> +} >> + >> static void hdp_v7_0_update_clock_gating(struct amdgpu_device *adev, >> bool enable) >> { >> @@ -126,7 +137,7 @@ static void hdp_v7_0_get_clockgating_state(struct amdgpu_device *adev, >> } >> >> const struct amdgpu_hdp_funcs hdp_v7_0_funcs = { >> - .flush_hdp = amdgpu_hdp_generic_flush, >> + .flush_hdp = hdp_v7_0_flush_hdp, >> .update_clock_gating = hdp_v7_0_update_clock_gating, >> .get_clock_gating_state = hdp_v7_0_get_clockgating_state, >> }; >> -- >> 2.49.0 >>