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[94.27.152.162]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-43fe4e3a18csm7750448f8f.20.2026.04.17.12.35.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 17 Apr 2026 12:35:57 -0700 (PDT) From: Timur =?UTF-8?B?S3Jpc3TDs2Y=?= To: Alex Hung Cc: Roman Li , amd-gfx list , "Deucher, Alexander" , Harry Wentland , Leo Li , Aurabindo Pillai Subject: Re: [PATCH] drm/amd/display: Restore analog connector support Date: Fri, 17 Apr 2026 21:35:56 +0200 Message-ID: <2356837.vFx2qVVIhK@timur-hyperion> In-Reply-To: References: <20260415224150.1807020-1-Roman.Li@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" Hi, Tested this on the following: HD 7870 XT - works R9 280X (Tahiti) - works R9 380X (Tonga) - works A10-7850K (Kaveri) - broken It seems that some other chunks of code were removed which were necessary f= or=20 external DP bridge encoders to work properly. Those will need to be added b= ack=20 too, otherwise we regress Kaveri APUs. Best regards, Timur On Thursday, April 16, 2026 7:38:39=E2=80=AFPM Central European Summer Time= Timur=20 Krist=C3=B3f wrote: > Hi, >=20 > I'll test this on a few different old GPUs and get back to you. >=20 > Thanks, > Timur >=20 > Alex Hung ezt =C3=ADrta (id=C5=91pont: 2026. =C3=A1pr= =2E 16., Cs=C3=BC 17:46): > > Reviewed-by: Alex Hung > >=20 > > On 4/15/26 16:41, Roman.Li@amd.com wrote: > > > From: Roman Li > > >=20 > > > [Why] > > > The analog connector support was accidentally removed, > > > causing a crash when connecting an analog monitor. > > >=20 > > > [How] > > > This patch restores the functions and pointers required for proper > > > analog > > > and DP bridge encoder support on legacy GPUs. > > >=20 > > > Fixes: 66715fc0ecfd ("drm/amd/display: Sync dcn42 with DC 3.2.373") > > > Cc: Timur Krist=C3=B3f > > > Signed-off-by: Roman Li > > > --- > > >=20 > > > .../amd/display/dc/hwss/dce110/dce110_hwseq.c | 53 ++++++++++++++++= +++ > > > 1 file changed, 53 insertions(+) > > >=20 > > > diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c > >=20 > > b/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c > >=20 > > > index 5273ca09fe12..e76abc877f4a 100644 > > > --- a/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c > > > +++ b/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c > > > @@ -677,6 +677,48 @@ dce110_dac_encoder_control(struct pipe_ctx > >=20 > > *pipe_ctx, bool enable) > >=20 > > > bios->funcs->encoder_control(bios, &encoder_control); > > > =20 > > > } > > >=20 > > > +static void > > > +dce110_external_encoder_control(enum bp_external_encoder_control_act= ion > >=20 > > action, > >=20 > > > + struct dc_link *link, > > > + struct dc_crtc_timing *timing) > > > +{ > > > + struct dc *dc =3D link->ctx->dc; > > > + struct dc_bios *bios =3D link->ctx->dc_bios; > > > + const struct dc_link_settings *link_settings =3D > >=20 > > &link->cur_link_settings; > >=20 > > > + enum bp_result bp_result =3D BP_RESULT_OK; > > > + struct bp_external_encoder_control ext_cntl =3D { > > > + .action =3D action, > > > + .connector_obj_id =3D link->link_enc->connector, > > > + .encoder_id =3D link->ext_enc_id, > > > + .lanes_number =3D link_settings->lane_count, > > > + .link_rate =3D link_settings->link_rate, > > > + > > > + /* Use signal type of the real link encoder, ie. DP */ > > > + .signal =3D link->connector_signal, > > > + > > > + /* We don't know the timing yet when executing the SETUP > >=20 > > action, > >=20 > > > + * so use a reasonably high default value. It seems that > >=20 > > ENABLE > >=20 > > > + * can change the actual pixel clock but doesn't work w= ith > >=20 > > higher > >=20 > > > + * pixel clocks than what SETUP was called with. > > > + */ > >=20 > > > + .pixel_clock =3D timing ? timing->pix_clk_100hz / 10 : > > 300000, > >=20 > > > + .color_depth =3D timing ? timing->display_color_depth : > > COLOR_DEPTH_888, > >=20 > > > + }; > > > + DC_LOGGER_INIT(dc->ctx); > > > + > > > + bp_result =3D bios->funcs->external_encoder_control(bios, > > > &ext_cntl); > > > + > > > + if (bp_result !=3D BP_RESULT_OK) > >=20 > > > + DC_LOG_ERROR("Failed to execute external encoder action: > > 0x%x\n", action); > >=20 > > > +} > > > + > > > +static void > > > +dce110_prepare_ddc(struct dc_link *link) > > > +{ > > > + if (link->ext_enc_id.id) > > > + > > =20 > > dce110_external_encoder_control(EXTERNAL_ENCODER_CONTROL_DDC_SETUP, li= nk, > >=20 > > NULL); > >=20 > > > +} > > > + > > >=20 > > > static bool > > > dce110_dac_load_detect(struct dc_link *link) > > > { > > >=20 > > > @@ -3376,6 +3418,15 @@ void dce110_enable_tmds_link_output(struct > >=20 > > dc_link *link, > >=20 > > > link->phy_state.symclk_state =3D SYMCLK_ON_TX_ON; > > > =20 > > > } > > >=20 > > > +static void dce110_enable_analog_link_output( > > > + struct dc_link *link, > > > + uint32_t pix_clk_100hz) > > > +{ > > > + link->link_enc->funcs->enable_analog_output( > > > + link->link_enc, > > > + pix_clk_100hz); > > > +} > > > + > > >=20 > > > void dce110_enable_dp_link_output( > > > =20 > > > struct dc_link *link, > > > const struct link_resource *link_res, > > >=20 > > > @@ -3513,8 +3564,10 @@ static const struct hw_sequencer_funcs > >=20 > > dce110_funcs =3D { > >=20 > > > .enable_lvds_link_output =3D dce110_enable_lvds_link_output, > > > .enable_tmds_link_output =3D dce110_enable_tmds_link_output, > > > .enable_dp_link_output =3D dce110_enable_dp_link_output, > > >=20 > > > + .enable_analog_link_output =3D dce110_enable_analog_link_output, > > >=20 > > > .disable_link_output =3D dce110_disable_link_output, > > > .dac_load_detect =3D dce110_dac_load_detect, > > >=20 > > > + .prepare_ddc =3D dce110_prepare_ddc, > > >=20 > > > }; > > > =20 > > > static const struct hwseq_private_funcs dce110_private_funcs =3D {