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[84.0.24.43]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-48048b49880sm59781895e9.11.2026.01.22.07.01.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 Jan 2026 07:01:25 -0800 (PST) From: Timur =?UTF-8?B?S3Jpc3TDs2Y=?= To: amd-gfx@lists.freedesktop.org Cc: Jon Doron , stable@vger.kernel.org, Alex Deucher , Alex Deucher Subject: Re: [PATCH] drm/amdgpu: fix NULL pointer dereference in amdgpu_gmc_filter_faults_remove Date: Thu, 22 Jan 2026 16:01:24 +0100 Message-ID: <2808451.vuYhMxLoTh@timur-hyperion> In-Reply-To: <20260121182447.2434085-1-alexander.deucher@amd.com> References: <20260121182447.2434085-1-alexander.deucher@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" On Wednesday, January 21, 2026 7:24:47=E2=80=AFPM Central European Standard= Time Alex=20 Deucher wrote: > From: Jon Doron >=20 > On APUs such as Raven and Renoir (GC 9.1.0, 9.2.2, 9.3.0), the ih1 and > ih2 interrupt ring buffers are not initialized. This is by design, as > these secondary IH rings are only available on discrete GPUs. See > vega10_ih_sw_init() which explicitly skips ih1/ih2 initialization when > AMD_IS_APU is set. >=20 > However, amdgpu_gmc_filter_faults_remove() unconditionally uses ih1 to > get the timestamp of the last interrupt entry. When retry faults are > enabled on APUs (noretry=3D0), this function is called from the SVM page > fault recovery path, resulting in a NULL pointer dereference when > amdgpu_ih_decode_iv_ts_helper() attempts to access ih->ring[]. >=20 > The crash manifests as: >=20 > BUG: kernel NULL pointer dereference, address: 0000000000000004 > RIP: 0010:amdgpu_ih_decode_iv_ts_helper+0x22/0x40 [amdgpu] > Call Trace: > amdgpu_gmc_filter_faults_remove+0x60/0x130 [amdgpu] > svm_range_restore_pages+0xae5/0x11c0 [amdgpu] > amdgpu_vm_handle_fault+0xc8/0x340 [amdgpu] > gmc_v9_0_process_interrupt+0x191/0x220 [amdgpu] > amdgpu_irq_dispatch+0xed/0x2c0 [amdgpu] > amdgpu_ih_process+0x84/0x100 [amdgpu] >=20 > This issue was exposed by commit 1446226d32a4 ("drm/amdgpu: Remove GC HW > IP 9.3.0 from noretry=3D1") which changed the default for Renoir APU from > noretry=3D1 to noretry=3D0, enabling retry fault handling and thus > exercising the buggy code path. >=20 > Fix this by adding a check for ih1.ring_size before attempting to use > it. Also restore the soft_ih support from commit dd299441654f ("drm/amdgp= u: > Rework retry fault removal"). This is needed if the hardware doesn't > support secondary HW IH rings. >=20 > v2: additional updates (Alex) >=20 > Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/3814 > Fixes: dd299441654f ("drm/amdgpu: Rework retry fault removal") > Cc: stable@vger.kernel.org > Signed-off-by: Jon Doron > Signed-off-by: Alex Deucher Reviewed-by: Timur Krist=C3=B3f Thank you for taking care of this! > --- > drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c | 7 ++++++- > 1 file changed, 6 insertions(+), 1 deletion(-) >=20 > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c > b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c index > 8e65fec9f534e..243d75917458a 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c > @@ -498,8 +498,13 @@ void amdgpu_gmc_filter_faults_remove(struct > amdgpu_device *adev, uint64_t addr, >=20 > if (adev->irq.retry_cam_enabled) > return; > + else if (adev->irq.ih1.ring_size) > + ih =3D &adev->irq.ih1; > + else if (adev->irq.ih_soft.enabled) > + ih =3D &adev->irq.ih_soft; > + else > + return; >=20 > - ih =3D &adev->irq.ih1; > /* Get the WPTR of the last entry in IH ring */ > last_wptr =3D amdgpu_ih_get_wptr(adev, ih); > /* Order wptr with ring data. */