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[2001:4c4e:24ef:ec00:33ed:eb5c:97a7:ed1d]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-43fe4e4d112sm5182040f8f.29.2026.04.17.07.09.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 17 Apr 2026 07:09:03 -0700 (PDT) From: Timur =?UTF-8?B?S3Jpc3TDs2Y=?= To: Christian =?UTF-8?B?S8O2bmln?= , Alex Deucher Cc: amd-gfx@lists.freedesktop.org, alexander.deucher@amd.com Subject: Re: [PATCH 7/7] drm/amdgpu/gfx6: Support harvested SI chips with disabled TCCs Date: Fri, 17 Apr 2026 16:09:02 +0200 Message-ID: <2835381.vuYhMxLoTh@timur-max> In-Reply-To: References: <20260416202643.25350-1-timur.kristof@gmail.com> <89ea2f13-57aa-4a9d-98b3-f5693e33c13a@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" On 2026. =C3=A1prilis 17., p=C3=A9ntek 15:36:20 k=C3=B6z=C3=A9p-eur=C3=B3pa= i ny=C3=A1ri id=C5=91 Alex Deucher=20 wrote: > > > +static void gfx_v6_0_setup_tcc(struct amdgpu_device *adev) > > > +{ > > > + u32 i, tcc, tcp_addr_config, num_active_tcc =3D 0; > > > + u64 chan_steer, patched_chan_steer =3D 0; > > > + const u32 num_max_tcc =3D > > > adev->gfx.config.max_texture_channel_caches; > > > + const u32 dis_tcc_mask =3D amdgpu_gfx_create_bitmask(num_max_tc= c) & > > > + REG_GET_FIELD(RREG32(mmCGTS_TCC_DISABL= E), > > > + CGTS_TCC_DISABLE, > > > TCC_DISABLE); > I would OR dis_tcc_mask with mmCGTS_USER_TCC_DISABLE as well in case > someone has set additional TCCs to disable as well. Other than that, > looks good to me. Thank you, will do. I'll split off the VCE patches into a separate series and send a second ver= sion=20 of this series with the consideration for CGTS_USER_TCC_DISABLE added. Timur