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([2a02:908:1252:fb60:be8a:bd56:1f94:86e7]) by smtp.gmail.com with ESMTPSA id dn16sm4297129edb.19.2020.11.13.07.31.21 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 13 Nov 2020 07:31:21 -0800 (PST) Subject: Re: [PATCH] drm/amdgpu: enable 48-bit IH timestamp counter To: "Sierra Guiza, Alejandro (Alex)" , "amd-gfx@lists.freedesktop.org" , "Koenig, Christian" References: <20201110175519.21308-1-alex.sierra@amd.com> From: =?UTF-8?Q?Christian_K=c3=b6nig?= Message-ID: <288f55c4-62a4-0249-7a9c-9dc417caa462@gmail.com> Date: Mon, 16 Nov 2020 12:31:20 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 MIME-Version: 1.0 In-Reply-To: Content-Language: en-US X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: christian.koenig@amd.com Cc: "Kuehling, Felix" Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" Feel free to keep my rb for this, but is 455 days enough in general or should we add wrap around handling? Christian. Am 10.11.20 um 18:57 schrieb Sierra Guiza, Alejandro (Alex): > [AMD Public Use] > > I just added support for vega10_ih too. > > Regards, > Alex > >> -----Original Message----- >> From: Sierra Guiza, Alejandro (Alex) >> Sent: Tuesday, November 10, 2020 11:55 AM >> To: amd-gfx@lists.freedesktop.org >> Cc: Koenig, Christian ; Kuehling, Felix >> ; Sierra Guiza, Alejandro (Alex) >> >> Subject: [PATCH] drm/amdgpu: enable 48-bit IH timestamp counter >> >> By default this timestamp is based on a 32 bit counter. >> This is used by the amdgpu_gmc_filter_faults, to avoid process the same >> interrupt in retry configuration. >> Apparently there's a problem when the timestamp coming from IH overflows >> and compares against timestamp coming from the the hash table. >> This patch only extends the time overflow from 10 minutes to aprx 455 days. >> >> Signed-off-by: Alex Sierra >> --- >> drivers/gpu/drm/amd/amdgpu/navi10_ih.c | 6 ++++++ >> drivers/gpu/drm/amd/amdgpu/vega10_ih.c | 6 ++++++ >> 2 files changed, 12 insertions(+) >> >> diff --git a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c >> b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c >> index 837769fcb35b..bda916f33805 100644 >> --- a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c >> +++ b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c >> @@ -94,6 +94,8 @@ static void navi10_ih_enable_interrupts(struct >> amdgpu_device *adev) >> >> ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 1); >> ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, >> 1); >> + ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, >> + RB_GPU_TS_ENABLE, 1); >> if (amdgpu_sriov_vf(adev) && adev->asic_type < CHIP_NAVI10) { >> if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL, >> ih_rb_cntl)) { >> DRM_ERROR("PSP program IH_RB_CNTL failed!\n"); >> @@ -109,6 +111,8 @@ static void navi10_ih_enable_interrupts(struct >> amdgpu_device *adev) >> ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, >> mmIH_RB_CNTL_RING1); >> ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING1, >> RB_ENABLE, 1); >> + ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING1, >> + RB_GPU_TS_ENABLE, 1); >> if (amdgpu_sriov_vf(adev) && adev->asic_type < >> CHIP_NAVI10) { >> if (psp_reg_program(&adev->psp, >> PSP_REG_IH_RB_CNTL_RING1, >> ih_rb_cntl)) { >> @@ -125,6 +129,8 @@ static void navi10_ih_enable_interrupts(struct >> amdgpu_device *adev) >> ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, >> mmIH_RB_CNTL_RING2); >> ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING2, >> RB_ENABLE, 1); >> + ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING2, >> + RB_GPU_TS_ENABLE, 1); >> if (amdgpu_sriov_vf(adev) && adev->asic_type < >> CHIP_NAVI10) { >> if (psp_reg_program(&adev->psp, >> PSP_REG_IH_RB_CNTL_RING2, >> ih_rb_cntl)) { >> diff --git a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c >> b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c >> index 407c6093c2ec..35d68bc5d95e 100644 >> --- a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c >> +++ b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c >> @@ -50,6 +50,8 @@ static void vega10_ih_enable_interrupts(struct >> amdgpu_device *adev) >> >> ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 1); >> ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, >> 1); >> + ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, >> + RB_GPU_TS_ENABLE, 1); >> if (amdgpu_sriov_vf(adev)) { >> if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL, >> ih_rb_cntl)) { >> DRM_ERROR("PSP program IH_RB_CNTL failed!\n"); >> @@ -64,6 +66,8 @@ static void vega10_ih_enable_interrupts(struct >> amdgpu_device *adev) >> ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, >> mmIH_RB_CNTL_RING1); >> ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING1, >> RB_ENABLE, 1); >> + ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING1, >> + RB_GPU_TS_ENABLE, 1); >> if (amdgpu_sriov_vf(adev)) { >> if (psp_reg_program(&adev->psp, >> PSP_REG_IH_RB_CNTL_RING1, >> ih_rb_cntl)) { >> @@ -80,6 +84,8 @@ static void vega10_ih_enable_interrupts(struct >> amdgpu_device *adev) >> ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, >> mmIH_RB_CNTL_RING2); >> ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING2, >> RB_ENABLE, 1); >> + ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING2, >> + RB_GPU_TS_ENABLE, 1); >> if (amdgpu_sriov_vf(adev)) { >> if (psp_reg_program(&adev->psp, >> PSP_REG_IH_RB_CNTL_RING2, >> ih_rb_cntl)) { >> -- >> 2.17.1 > _______________________________________________ > amd-gfx mailing list > amd-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/amd-gfx _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx