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[165.204.72.6]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-35dd062edbcsm9403860f8f.84.2024.06.03.11.09.05 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 03 Jun 2024 11:09:05 -0700 (PDT) Message-ID: <29d354ec-2cbf-4249-8769-031e93183cb5@gmail.com> Date: Mon, 3 Jun 2024 20:09:03 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] drm/amdgpu: use local xcc write to flush tlb To: Yiqing Yao , amd-gfx@lists.freedesktop.org Cc: alexander.deucher@amd.com, christian.koenig@amd.com, haijun.chang@amd.com, horace.chen@amd.com References: <20240603114607.4143848-1-YiQing.Yao@amd.com> Content-Language: en-US From: =?UTF-8?Q?Christian_K=C3=B6nig?= In-Reply-To: <20240603114607.4143848-1-YiQing.Yao@amd.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" Am 03.06.24 um 13:46 schrieb Yiqing Yao: > When flushing gpu tlb using kiq from gfxhub, kiq ring is always > local as xcc instance is selected for it. Thus using lower 18 bits > to access mmregs inside local xcc instead of full address used > when accessing regs outside of local xcc. > > Remove redundent code. > > Signed-off-by: Yiqing Yao > --- > drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 6 ++++-- > 1 file changed, 4 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c > index 350f6b6676f1..864fea31c354 100644 > --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c > @@ -853,8 +853,10 @@ static void gmc_v9_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid, > */ > if (adev->gfx.kiq[inst].ring.sched.ready && > (amdgpu_sriov_runtime(adev) || !amdgpu_sriov_vf(adev))) { > - uint32_t req = hub->vm_inv_eng0_req + hub->eng_distance * eng; > - uint32_t ack = hub->vm_inv_eng0_ack + hub->eng_distance * eng; > + > + /* Select lower 18 bits to write in local xcc */ > + if (vmhub < AMDGPU_MMHUB0(0)) > + req = req & 0x3ffff; A bit more explanation would be good here, e.g. what you have in the commit message. Apart from that why do we need that in the first place? Isn't the KIQ able to access the register anyway? Regards, Christian. > > amdgpu_gmc_fw_reg_write_reg_wait(adev, req, ack, inv_req, > 1 << vmid, inst);