From: "Lazar, Lijo" <lijo.lazar@amd.com>
To: Jane Jian <Jane.Jian@amd.com>, Haijun.Chang@amd.com, Victor.Zhao@amd.com
Cc: amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH] drm/amdgpu: keep init xcc0 for all xccs under sriov
Date: Fri, 14 Jun 2024 17:20:20 +0530 [thread overview]
Message-ID: <2bf881e2-9db1-47f8-b8ec-dee5dd7a295e@amd.com> (raw)
In-Reply-To: <20240614111022.236072-1-Jane.Jian@amd.com>
On 6/14/2024 4:40 PM, Jane Jian wrote:
> [WHY]
> sriov has the higher bit violation when flushing tlb
>
> [HOW]
> for sriov only init XCC0(lower 16-bit) for all XCCs to avoid higher bit violation
> since kiq ring is always local, local address without XCC ID is enough to be sent to the XCC KIQ
>
The description is incorrect.
Bits 18:20 represent xcc id. To guarantee all paths pass a local
address, you should just strip bits 18:20 in kiq/rlcg read/write
functions rather than here.
Thanks,
Lijo
> Signed-off-by: Jane Jian <Jane.Jian@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c | 23 +++++++++++++++--------
> 1 file changed, 15 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c
> index e14acab5cceb..4e38a66a52f4 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c
> @@ -537,29 +537,36 @@ static void gfxhub_v1_2_xcc_init(struct amdgpu_device *adev, uint32_t xcc_mask)
> {
> struct amdgpu_vmhub *hub;
> int i;
> + uint32_t gc_index;
>
> for_each_inst(i, xcc_mask) {
> hub = &adev->vmhub[AMDGPU_GFXHUB(i)];
>
> + /* for sriov only init XCC0(lower 16-bit) to avoid higher bit violation */
> + if (amdgpu_sriov_vf(adev))
> + gc_index = 0;
> + else
> + gc_index = GET_INST(GC, i);
> +
> hub->ctx0_ptb_addr_lo32 =
> - SOC15_REG_OFFSET(GC, GET_INST(GC, i),
> + SOC15_REG_OFFSET(GC, gc_index,
> regVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32);
> hub->ctx0_ptb_addr_hi32 =
> - SOC15_REG_OFFSET(GC, GET_INST(GC, i),
> + SOC15_REG_OFFSET(GC, gc_index,
> regVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32);
> hub->vm_inv_eng0_sem =
> - SOC15_REG_OFFSET(GC, GET_INST(GC, i), regVM_INVALIDATE_ENG0_SEM);
> + SOC15_REG_OFFSET(GC, gc_index, regVM_INVALIDATE_ENG0_SEM);
> hub->vm_inv_eng0_req =
> - SOC15_REG_OFFSET(GC, GET_INST(GC, i), regVM_INVALIDATE_ENG0_REQ);
> + SOC15_REG_OFFSET(GC, gc_index, regVM_INVALIDATE_ENG0_REQ);
> hub->vm_inv_eng0_ack =
> - SOC15_REG_OFFSET(GC, GET_INST(GC, i), regVM_INVALIDATE_ENG0_ACK);
> + SOC15_REG_OFFSET(GC, gc_index, regVM_INVALIDATE_ENG0_ACK);
> hub->vm_context0_cntl =
> - SOC15_REG_OFFSET(GC, GET_INST(GC, i), regVM_CONTEXT0_CNTL);
> + SOC15_REG_OFFSET(GC, gc_index, regVM_CONTEXT0_CNTL);
> hub->vm_l2_pro_fault_status =
> - SOC15_REG_OFFSET(GC, GET_INST(GC, i),
> + SOC15_REG_OFFSET(GC, gc_index,
> regVM_L2_PROTECTION_FAULT_STATUS);
> hub->vm_l2_pro_fault_cntl =
> - SOC15_REG_OFFSET(GC, GET_INST(GC, i), regVM_L2_PROTECTION_FAULT_CNTL);
> + SOC15_REG_OFFSET(GC, gc_index, regVM_L2_PROTECTION_FAULT_CNTL);
>
> hub->ctx_distance = regVM_CONTEXT1_CNTL -
> regVM_CONTEXT0_CNTL;
next prev parent reply other threads:[~2024-06-14 11:50 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-06-14 11:10 [PATCH] drm/amdgpu: keep init xcc0 for all xccs under sriov Jane Jian
2024-06-14 11:50 ` Lazar, Lijo [this message]
2024-06-15 2:08 ` Lazar, Lijo
2024-06-17 3:28 ` Chang, HaiJun
2024-06-17 3:35 ` Lazar, Lijo
2024-06-17 4:56 ` Chang, HaiJun
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